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<20261019102824.3157044-7-damon.ding@rock-chips.com> References: <20261019102824.3157044-1-damon.ding@rock-chips.com> <20261019102824.3157044-7-damon.ding@rock-chips.com> Date: Mon, 19 Oct 2026 10:44:45 +0000 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MSBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIHBoeTogcm9ja2NoaXA6 IG1pc3Npbmcgc2V0X2xhbmVzIGhhbmRsaW5nIGluIHJvY2tjaGlwX2VkcF9waHlfY29uZmlndXJl KCkKLS0KCmNvbW1pdCAzMGY4OTk5ZDNlZWIyMDA3ZGM4NDE5NzllN2E0ODQxMDA0M2IwMDJiCkF1 dGhvcjogRGFtb24gRGluZyA8ZGFtb24uZGluZ0Byb2NrLWNoaXBzLmNvbT4KCmFybTY0OiBkdHM6 IHJvY2tjaGlwOiByazM1Nng6IEFkZCBlRFAgY29udHJvbGxlciBhbmQgcGh5IG5vZGVzCgpUaGlz IGNvbW1pdCBhZGRzIHRoZSBlRFAgUEhZIEdSRiAod2l0aCB0aGUgZURQIFBIWSBjaGlsZCBub2Rl KSBhbmQgdGhlIGVEUApjb250cm9sbGVyIGRldmljZSB0cmVlIG5vZGVzIGZvciB0aGUgUkszNTY4 IGFuZCBSSzM1NjYgU29Dcy4KCj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvYm9vdC9kdHMvcm9j a2NoaXAvcmszNTZ4LWJhc2UuZHRzaSBiL2FyY2gvYXJtNjQvYm9vdC9kdHMvcm9ja2NoaXAvcmsz NTZ4LWJhc2UuZHRzaQo+IGluZGV4IGE1ODMyODk1YmQzOTIuLjNiNjBlNDM1NWFkOGMgMTAwNjQ0 Cj4gLS0tIGEvYXJjaC9hcm02NC9ib290L2R0cy9yb2NrY2hpcC9yazM1NngtYmFzZS5kdHNpCj4g KysrIGIvYXJjaC9hcm02NC9ib290L2R0cy9yb2NrY2hpcC9yazM1NngtYmFzZS5kdHNpCj4gQEAg LTQwMyw2ICs0MDMsMjAgQEAgdXNiMnBoeTFfZ3JmOiBzeXNjb25AZmRjYTgwMDAgewo+ICAJCXJl ZyA9IDwweDAgMHhmZGNhODAwMCAweDAgMHg4MDAwPjsKPiAgCX07Cj4gIAo+ICsJZWRwX3BoeV9n cmY6IHN5c2NvbkBmZGNiMDAwMCB7Cj4gKwkJY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxyazM1Njgt ZWRwLXBoeS1ncmYiLCAic3lzY29uIiwgInNpbXBsZS1tZmQiOwo+ICsJCXJlZyA9IDwweDAgMHhm ZGNiMDAwMCAweDAgMHgxMDA+Owo+ICsJCWNsb2NrcyA9IDwmY3J1IFBDTEtfRURQUEhZX0dSRj47 Cj4gKwo+ICsJCWVkcF9waHk6IGVkcC1waHkgewo+ICsJCQljb21wYXRpYmxlID0gInJvY2tjaGlw LHJrMzU2OC1lZHAtcGh5IjsKPiArCQkJY2xvY2tzID0gPCZwbXVjcnUgWElOX09TQzBfRURQUEhZ X0c+Owo+ICsJCQljbG9jay1uYW1lcyA9ICJyZWZjbGsiOwo+ICsJCQkjcGh5LWNlbGxzID0gPDA+ Owo+ICsJCQlzdGF0dXMgPSAiZGlzYWJsZWQiOwo+ICsJCX07Cj4gKwl9Owo+ICsKPiAgCXBtdWNy dTogY2xvY2stY29udHJvbGxlckBmZGQwMDAwMCB7Cj4gIAkJY29tcGF0aWJsZSA9ICJyb2NrY2hp cCxyazM1NjgtcG11Y3J1IjsKPiAgCQlyZWcgPSA8MHgwIDB4ZmRkMDAwMDAgMHgwIDB4MTAwMD47 Cj4gQEAgLTg3OSw2ICs4OTMsMzMgQEAgaGRtaV9vdXQ6IHBvcnRAMSB7Cj4gIAkJfTsKPiAgCX07 Cj4gIAo+ICsJZWRwOiBlZHBAZmUwYzAwMDAgewo+ICsJCWNvbXBhdGlibGUgPSAicm9ja2NoaXAs cmszNTY4LWVkcCI7Cj4gKwkJcmVnID0gPDB4MCAweGZlMGMwMDAwIDB4MCAweDEwMDAwPjsKPiAr CQljbG9ja3MgPSA8JnBtdWNydSBYSU5fT1NDMF9FRFBQSFlfRz4sIDwmY3J1IFBDTEtfRURQX0NU Ukw+LCA8JmNydSBIQ0xLX1ZPPjsKPiArCQljbG9jay1uYW1lcyA9ICJkcCIsICJwY2xrIiwgImhj bGsiOwo+ICsJCWludGVycnVwdHMgPSA8R0lDX1NQSSAxOCBJUlFfVFlQRV9MRVZFTF9ISUdIPjsK PiArCQlwaHlzID0gPCZlZHBfcGh5PjsKPiArCQlwaHktbmFtZXMgPSAiZHAiOwoKW1NldmVyaXR5 OiBIaWdoXQpDYW4gdGhlIEFuYWxvZ2l4IGVEUCBjb250cm9sbGVyIGNvbXBsZXRlIGxpbmsgdHJh aW5pbmcgd2hlbiB3aXJlZCB0bwplZHBfcGh5ICgicm9ja2NoaXAscmszNTY4LWVkcC1waHkiKSB3 aXRob3V0IGhhbmRsaW5nIG9wdHMtPmRwLnNldF9sYW5lcyBpbgpyb2NrY2hpcF9lZHBfcGh5X2Nv bmZpZ3VyZSgpPwoKV2hlbiBhbmFsb2dpeF9kcF9saW5rX3N0YXJ0KCkgcnVucyBpbgpkcml2ZXJz L2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2FuYWxvZ2l4X2RwX2NvcmUuYywgaXQgY2FsbHMKYW5h bG9naXhfZHBfc2V0X2xpbmtfYmFuZHdpZHRoKCksIGFuYWxvZ2l4X2RwX3NldF9sYW5lX2NvdW50 KCksIGFuZAphbmFsb2dpeF9kcF9zZXRfbGFuZV9saW5rX3RyYWluaW5nKCkgaW4KZHJpdmVycy9n cHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9yZWcuYy4gRWFjaCBvZiB0aGVzZSBm dW5jdGlvbnMKemVyby1pbml0aWFsaXplcyBhIGxvY2FsIHVuaW9uIHBoeV9jb25maWd1cmVfb3B0 cyBwaHlfY2ZnID0gezB9IGFuZCBzZXRzCm9ubHkgc2V0X3JhdGUsIHNldF9sYW5lcywgb3Igc2V0 X3ZvbHRhZ2VzIGluZGl2aWR1YWxseToKCmRyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgv YW5hbG9naXhfZHBfcmVnLmM6CmFuYWxvZ2l4X2RwX3NldF9sYW5lX2xpbmtfdHJhaW5pbmcoKSB7 CglpZiAoZHAtPnBoeSkgewoJCXVuaW9uIHBoeV9jb25maWd1cmVfb3B0cyBwaHlfY2ZnID0gezB9 OwoKCQlmb3IgKGxhbmUgPSAwOyBsYW5lIDwgZHAtPmxpbmtfdHJhaW4ubGFuZV9jb3VudDsgbGFu ZSsrKSB7CgkJCS4uLgoJCQlwaHlfY2ZnLmRwLnZvbHRhZ2VbbGFuZV0gPSB2czsKCQkJcGh5X2Nm Zy5kcC5wcmVbbGFuZV0gPSBwZTsKCQl9CgoJCXBoeV9jZmcuZHAuc2V0X3ZvbHRhZ2VzID0gdHJ1 ZTsKCQlyZXQgPSBwaHlfY29uZmlndXJlKGRwLT5waHksICZwaHlfY2ZnKTsKCkhvd2V2ZXIsIGlu IGRyaXZlcnMvcGh5L3JvY2tjaGlwL3BoeS1yb2NrY2hpcC1uYW5lbmctZWRwLmMsCnJvY2tjaGlw X2VkcF9waHlfY29uZmlndXJlKCkgb25seSBjaGVja3Mgb3B0cy0+ZHAuc2V0X3JhdGUgYW5kCm9w dHMtPmRwLnNldF92b2x0YWdlczoKCmRyaXZlcnMvcGh5L3JvY2tjaGlwL3BoeS1yb2NrY2hpcC1u YW5lbmctZWRwLmM6CnJvY2tjaGlwX2VkcF9waHlfY29uZmlndXJlKCkgewoJaWYgKG9wdHMtPmRw LnNldF9yYXRlKSB7CgkJcmV0ID0gcm9ja2NoaXBfZWRwX3BoeV9zZXRfcmF0ZShlZHBwaHksICZv cHRzLT5kcCk7CgkJaWYgKHJldCkgewoJCQlkZXZfZXJyKGVkcHBoeS0+ZGV2LCAiRmFpbGVkIHRv IHNldCByYXRlXG4iKTsKCQkJcmV0dXJuIHJldDsKCQl9Cgl9CgoJaWYgKG9wdHMtPmRwLnNldF92 b2x0YWdlcykgewoJCXJldCA9IHJvY2tjaGlwX2VkcF9waHlfc2V0X3ZvbHRhZ2VzKGVkcHBoeSwg Jm9wdHMtPmRwKTsKCQlpZiAocmV0KSB7CgkJCWRldl9lcnIoZWRwcGh5LT5kZXYsICJGYWlsZWQg dG8gc2V0IHZvbHRhZ2VzXG4iKTsKCQkJcmV0dXJuIHJldDsKCQl9Cgl9CgpCZWNhdXNlIGVhY2gg cGh5X2NvbmZpZ3VyZSgpIGNhbGwgcGFzc2VzIGEgZnJlc2ggc3RydWN0IHdpdGggb25seSBvbmUK YWN0aW9uIGZsYWcgc2V0OgoKMS4gSW4gYW5hbG9naXhfZHBfc2V0X2xpbmtfYmFuZHdpZHRoKCks IHBoeV9jZmcuZHAuc2V0X3JhdGUgaXMgdHJ1ZSB3aGlsZQpwaHlfY2ZnLmRwLmxhbmVzIGlzIDAu IHJvY2tjaGlwX2VkcF9waHlfdmVyaWZ5X2NvbmZpZygpIHNraXBzIHRoZSBsYW5lcwpjaGVjayBi ZWNhdXNlIGRwLT5zZXRfbGFuZXMgaXMgZmFsc2UsIGFuZCByb2NrY2hpcF9lZHBfcGh5X3NldF9y YXRlKCkgdGhlbgpldmFsdWF0ZXMgfkdFTk1BU0soZHAtPmxhbmVzIC0gMSwgMCkgd2l0aCBkcC0+ bGFuZXMgPT0gMCwgdW5kZXJmbG93aW5nCmRwLT5sYW5lcyAtIDEgd2hlbiBwcm9ncmFtbWluZyBF RFBfUEhZX1RYX1BEX01BU0sgYW5kIEVEUF9QSFlfVFhfSURMRV9NQVNLOgoKZHJpdmVycy9waHkv cm9ja2NoaXAvcGh5LXJvY2tjaGlwLW5hbmVuZy1lZHAuYzoKcm9ja2NoaXBfZWRwX3BoeV9zZXRf cmF0ZSgpIHsKCXJlZ21hcF93cml0ZShlZHBwaHktPmdyZiwgRURQX1BIWV9HUkZfQ09OMCwKCQkg ICAgIEZJRUxEX1BSRVBfV00xNihFRFBfUEhZX1BEX1BMTF9NQVNLLCAwKSk7CglyZWdtYXBfd3Jp dGUoZWRwcGh5LT5ncmYsIEVEUF9QSFlfR1JGX0NPTjAsCgkJICAgICBGSUVMRF9QUkVQX1dNMTYo RURQX1BIWV9UWF9QRF9NQVNLLCB+R0VOTUFTSyhkcC0+bGFuZXMgLSAxLCAwKSkpOwoJLi4uCgly ZWdtYXBfd3JpdGUoZWRwcGh5LT5ncmYsIEVEUF9QSFlfR1JGX0NPTjAsCgkJICAgICBGSUVMRF9Q UkVQX1dNMTYoRURQX1BIWV9UWF9JRExFX01BU0ssIH5HRU5NQVNLKGRwLT5sYW5lcyAtIDEsIDAp KSk7CgoyLiBJbiBhbmFsb2dpeF9kcF9zZXRfbGFuZV9jb3VudCgpLCBwaHlfY2ZnLmRwLnNldF9s YW5lcyBpcyB0cnVlIGFuZApwaHlfY2ZnLmRwLmxhbmVzIGhvbGRzIHRoZSBsYW5lIGNvdW50LCBi dXQgcm9ja2NoaXBfZWRwX3BoeV9jb25maWd1cmUoKQppZ25vcmVzIG9wdHMtPmRwLnNldF9sYW5l cywgbmVpdGhlciBzYXZpbmcgdGhlIGxhbmUgY291bnQgbm9yIHVwZGF0aW5nIHRoZQpsYW5lIHBv d2VyIGFuZCBpZGxlIG1hc2tzLgoKMy4gSW4gYW5hbG9naXhfZHBfc2V0X2xhbmVfbGlua190cmFp bmluZygpLCBwaHlfY2ZnLmRwLnNldF92b2x0YWdlcyBpcyB0cnVlCndoaWxlIHBoeV9jZmcuZHAu bGFuZXMgaXMgMCwgc28gcm9ja2NoaXBfZWRwX3BoeV9zZXRfdm9sdGFnZXMoKSBsb29wcyBmcm9t CjAgdG8gZHAtPmxhbmVzICgwKSBhbmQgbmV2ZXIgd3JpdGVzIHRoZSB2b2x0YWdlIHN3aW5nIG9y IHByZS1lbXBoYXNpcwpzZXR0aW5nczoKCmRyaXZlcnMvcGh5L3JvY2tjaGlwL3BoeS1yb2NrY2hp cC1uYW5lbmctZWRwLmM6CnJvY2tjaGlwX2VkcF9waHlfc2V0X3ZvbHRhZ2VzKCkgewoJdTggbGFu ZTsKCglmb3IgKGxhbmUgPSAwOyBsYW5lIDwgZHAtPmxhbmVzOyBsYW5lKyspCgkJcm9ja2NoaXBf ZWRwX3BoeV9zZXRfdm9sdGFnZShlZHBwaHksIGRwLCBsYW5lKTsKCglyZXR1cm4gMDsKfQoKU2hv dWxkIHRoZSBOYW5lbmcgZURQIFBIWSBkcml2ZXIgaGFuZGxlIG9wdHMtPmRwLnNldF9sYW5lcyBh bmQgY2FjaGUgdGhlCmNvbmZpZ3VyZWQgbGFuZSBjb3VudCBpbiBzdHJ1Y3Qgcm9ja2NoaXBfZWRw X3BoeSBzbyB0aGF0IHNlcGFyYXRlCnNldF9yYXRlLCBzZXRfbGFuZXMsIGFuZCBzZXRfdm9sdGFn ZXMgY2FsbHMgZnJvbSB0aGUgQW5hbG9naXggRFAgY29udHJvbGxlcgp3b3JrIHByb3Blcmx5PwoK PiArCQlwb3dlci1kb21haW5zID0gPCZwb3dlciBSSzM1NjhfUERfVk8+Owo+ICsJCXJlc2V0cyA9 IDwmY3J1IFNSU1RfRURQXzI0TT4sIDwmY3J1IFNSU1RfUF9FRFBfQ1RSTD47Cj4gKwkJcmVzZXQt bmFtZXMgPSAiZHAiLCAiYXBiIjsKPiArCQlzdGF0dXMgPSAiZGlzYWJsZWQiOwpbIC4uLiBdCgot LSAKU2FzaGlrbyBBSSByZXZpZXcgwrcgaHR0cHM6Ly9zYXNoaWtvLmRldi8jL3BhdGNoc2V0LzIw MjYxMDE5MTAyODI0LjMxNTcwNDQtMS1kYW1vbi5kaW5nQHJvY2stY2hpcHMuY29tP3BhcnQ9NgoK LS0gCmxpbnV4LXBoeSBtYWlsaW5nIGxpc3QKbGludXgtcGh5QGxpc3RzLmluZnJhZGVhZC5vcmcK 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9oMSHBJakoKop1MJ+yzKGQmqx4U/bMgc9jHlkx3hsHHaj+OblShkwVS48f5AVvSz25 ye07osH3uD5pLaQK7jEc+lceM9heHJz/6moUbDJIytfKUnswE/+E0HTR+MPF1Mh5s6 r8uxRuRyg/0ItHtxaY7mmQ2AR5B0AWOmJ7yrdj2Alius5e3ggpYgVBtc1S2V6DPk25 RAKkPVibWA6j5ZHsEqOfGB1LTSKnbyKclG6HBn78gnFeB4MtONII27LvTrSegXSsQo M/AXuFmmCMcmQ== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v2 6/6] arm64: dts: rockchip: rk356x: Add eDP controller and phy nodes Reply-To: sashiko-reviews@lists.linux.dev To: "Damon Ding" Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261019102824.3157044-7-damon.ding@rock-chips.com> References: <20261019102824.3157044-1-damon.ding@rock-chips.com> <20261019102824.3157044-7-damon.ding@rock-chips.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Mon, 19 Oct 2026 10:44:45 +0000 Precedence: bulk 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Sashiko AI review found 1 potential issue(= s) to consider: - [High] phy: rockchip: missing set_lanes handling in rockchip_edp_phy_conf= igure() -- commit 30f8999d3eeb2007dc841979e7a48410043b002b Author: Damon Ding arm64: dts: rockchip: rk356x: Add eDP controller and phy nodes This commit adds the eDP PHY GRF (with the eDP PHY child node) and the eDP controller device tree nodes for the RK3568 and RK3566 SoCs. > diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/b= oot/dts/rockchip/rk356x-base.dtsi > index a5832895bd392..3b60e4355ad8c 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi > @@ -403,6 +403,20 @@ usb2phy1_grf: syscon@fdca8000 { > reg =3D <0x0 0xfdca8000 0x0 0x8000>; > }; > =20 > + edp_phy_grf: syscon@fdcb0000 { > + compatible =3D "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; > + reg =3D <0x0 0xfdcb0000 0x0 0x100>; > + clocks =3D <&cru PCLK_EDPPHY_GRF>; > + > + edp_phy: edp-phy { > + compatible =3D "rockchip,rk3568-edp-phy"; > + clocks =3D <&pmucru XIN_OSC0_EDPPHY_G>; > + clock-names =3D "refclk"; > + #phy-cells =3D <0>; > + status =3D "disabled"; > + }; > + }; > + > pmucru: clock-controller@fdd00000 { > compatible =3D "rockchip,rk3568-pmucru"; > reg =3D <0x0 0xfdd00000 0x0 0x1000>; > @@ -879,6 +893,33 @@ hdmi_out: port@1 { > }; > }; > =20 > + edp: edp@fe0c0000 { > + compatible =3D "rockchip,rk3568-edp"; > + reg =3D <0x0 0xfe0c0000 0x0 0x10000>; > + clocks =3D <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>, <&cru HC= LK_VO>; > + clock-names =3D "dp", "pclk", "hclk"; > + interrupts =3D ; > + phys =3D <&edp_phy>; > + phy-names =3D "dp"; [Severity: High] Can the Analogix eDP controller complete link training when wired to edp_phy ("rockchip,rk3568-edp-phy") without handling opts->dp.set_lanes in rockchip_edp_phy_configure()? When analogix_dp_link_start() runs in drivers/gpu/drm/bridge/analogix/analogix_dp_core.c, it calls analogix_dp_set_link_bandwidth(), analogix_dp_set_lane_count(), and analogix_dp_set_lane_link_training() in drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c. Each of these functions zero-initializes a local union phy_configure_opts phy_cfg =3D {0} and sets only set_rate, set_lanes, or set_voltages individually: drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c: analogix_dp_set_lane_link_training() { if (dp->phy) { union phy_configure_opts phy_cfg =3D {0}; for (lane =3D 0; lane < dp->link_train.lane_count; lane++) { ... phy_cfg.dp.voltage[lane] =3D vs; phy_cfg.dp.pre[lane] =3D pe; } phy_cfg.dp.set_voltages =3D true; ret =3D phy_configure(dp->phy, &phy_cfg); However, in drivers/phy/rockchip/phy-rockchip-naneng-edp.c, rockchip_edp_phy_configure() only checks opts->dp.set_rate and opts->dp.set_voltages: drivers/phy/rockchip/phy-rockchip-naneng-edp.c: rockchip_edp_phy_configure() { if (opts->dp.set_rate) { ret =3D rockchip_edp_phy_set_rate(edpphy, &opts->dp); if (ret) { dev_err(edpphy->dev, "Failed to set rate\n"); return ret; } } if (opts->dp.set_voltages) { ret =3D rockchip_edp_phy_set_voltages(edpphy, &opts->dp); if (ret) { dev_err(edpphy->dev, "Failed to set voltages\n"); return ret; } } Because each phy_configure() call passes a fresh struct with only one action flag set: 1. In analogix_dp_set_link_bandwidth(), phy_cfg.dp.set_rate is true while phy_cfg.dp.lanes is 0. rockchip_edp_phy_verify_config() skips the lanes check because dp->set_lanes is false, and rockchip_edp_phy_set_rate() then evaluates ~GENMASK(dp->lanes - 1, 0) with dp->lanes =3D=3D 0, underflowing dp->lanes - 1 when programming EDP_PHY_TX_PD_MASK and EDP_PHY_TX_IDLE_MASK: drivers/phy/rockchip/phy-rockchip-naneng-edp.c: rockchip_edp_phy_set_rate() { regmap_write(edpphy->grf, EDP_PHY_GRF_CON0, FIELD_PREP_WM16(EDP_PHY_PD_PLL_MASK, 0)); regmap_write(edpphy->grf, EDP_PHY_GRF_CON0, FIELD_PREP_WM16(EDP_PHY_TX_PD_MASK, ~GENMASK(dp->lanes - 1, 0))); ... regmap_write(edpphy->grf, EDP_PHY_GRF_CON0, FIELD_PREP_WM16(EDP_PHY_TX_IDLE_MASK, ~GENMASK(dp->lanes - 1, 0))); 2. In analogix_dp_set_lane_count(), phy_cfg.dp.set_lanes is true and phy_cfg.dp.lanes holds the lane count, but rockchip_edp_phy_configure() ignores opts->dp.set_lanes, neither saving the lane count nor updating the lane power and idle masks. 3. In analogix_dp_set_lane_link_training(), phy_cfg.dp.set_voltages is true while phy_cfg.dp.lanes is 0, so rockchip_edp_phy_set_voltages() loops from 0 to dp->lanes (0) and never writes the voltage swing or pre-emphasis settings: drivers/phy/rockchip/phy-rockchip-naneng-edp.c: rockchip_edp_phy_set_voltages() { u8 lane; for (lane =3D 0; lane < dp->lanes; lane++) rockchip_edp_phy_set_voltage(edpphy, dp, lane); return 0; } Should the Naneng eDP PHY driver handle opts->dp.set_lanes and cache the configured lane count in struct rockchip_edp_phy so that separate set_rate, set_lanes, and set_voltages calls from the Analogix DP controller work properly? > + power-domains =3D <&power RK3568_PD_VO>; > + resets =3D <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; > + reset-names =3D "dp", "apb"; > + status =3D "disabled"; [ ... ] --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261019102824.3157= 044-1-damon.ding@rock-chips.com?part=3D6