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Sashiko AI review found 1 potential issue(= s) to consider: - [Medium] clk: tegra: _calc_rate() always fails with -EINVAL for 48MHz par= ent_rate -- commit 5b85244997fd59cc85d760a4c82ed76c458e3f43 Author: Dmitry Osipenko clk: tegra: support 48MHz clock for pll_p_out1 This patch adds 48 MHz parent rate handling in _calc_rate() to avoid hitting a BUG() when UEFI configures pll_p_out1 to 48 MHz on Surface 2. > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c > index 591b9f0c155a0..e48ca3f4b5f86 100644 > --- a/drivers/clk/tegra/clk-pll.c > +++ b/drivers/clk/tegra/clk-pll.c > @@ -575,6 +575,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra= _clk_pll_freq_table *cfg, > break; > case 9600000: > case 28800000: > + case 48000000: > /* > * PLL_P_OUT1 rate is not listed in PLLA table > */ [Severity: Medium] When parent_rate is 48000000, this switch arm in _calc_rate() in drivers/clk/tegra/clk-pll.c computes: cfreq =3D parent_rate / (parent_rate / 1000000); which evaluates to 1000000 (1 MHz). Later in _calc_rate(), cfg->m is calculated and validated against divm_max(pll): cfg->m =3D parent_rate / cfreq; cfg->n =3D cfg->output_rate / cfreq; cfg->cpcon =3D OUT_OF_TABLE_CPCON; if (cfg->m =3D=3D 0 || cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || cfg->output_rate > pll->params->vco_max) { return -EINVAL; } For parent_rate =3D=3D 48000000 and cfreq =3D=3D 1000000, cfg->m is 48. How= ever, pll_a uses a 5-bit input divider across Tegra114/124 (via pllp_nmp in drivers/clk/tegra/clk-tegra114.c) and Tegra20/30 (via default_nmp in drivers/clk/tegra/clk-pll.c): static struct div_nmp pllp_nmp =3D { .divm_shift =3D 0, .divm_width =3D 5, ... }; Because divm_max(pll) is 31, cfg->m > divm_max(pll) is always true when cfg->m is 48. When UEFI sets pll_p_out1 to 48 MHz, won't _calc_rate() unconditionally return -EINVAL whenever clk_pll_set_rate() or clk_pll_determine_rate() is called on pll_a, causing tegra114_clock_init() -> tegra_clk_apply_init_tabl= e() -> tegra_init_from_table() in drivers/clk/tegra/clk.c to fail to configure TEGRA114_CLK_PLL_A and hit WARN_ON(1)? if (tbl->rate) if (clk_set_rate(clk, tbl->rate)) { pr_err("%s: Failed to set rate %lu of %s\n", __func__, tbl->rate, __clk_get_name(clk)); WARN_ON(1); } --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261019135441.1420= 968-333-sashal@kernel.org?part=3D1