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From: sashiko-bot@kernel.org
To: "Vyacheslav Yurkov" <V.Yurkov.EXT@bruker.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: bus: Add Altera AXI Timeout Bridge
Date: Wed, 21 Oct 2026 20:05:08 +0000	[thread overview]
Message-ID: <sashiko-outbox-180625@kernel.org> (raw)
In-Reply-To: <20261021-feature-timeout-ip-v2-1-a037be089518@bruker.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dt-bindings: bus: undocumented compatible in axi-timeout-bridge example
- [Low] dt-bindings: bus: non-canonical property order in axi-timeout-bridge example
--

commit b1b42eb61f1fec5cade8d2ad793870c54e4f6574
Author: Vyacheslav Yurkov <V.Yurkov.EXT@bruker.com>

dt-bindings: bus: Add Altera AXI Timeout Bridge

This commit adds the devicetree binding schema for the Altera AXI Timeout
Bridge FPGA IP core, which monitors AXI transactions to downstream fabric
peripherals and terminates timed-out accesses with an error response and
interrupt.

> diff --git a/Documentation/devicetree/bindings/bus/altr,axi-timeout-bridge-1.0.yaml b/Documentation/devicetree/bindings/bus/altr,axi-timeout-bridge-1.0.yaml
> new file mode 100644
> index 0000000000000..3512494442d46
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/altr,axi-timeout-bridge-1.0.yaml
> @@ -0,0 +1,80 @@

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    timeout-bridge@10000 {
> +        compatible = "altr,axi-timeout-bridge-1.0";
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +
> +        reg = <0x10000 0x10>;
> +        interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
> +        ranges = <0x0 0x10010 0x1000>;

[Severity: Low]
In Documentation/devicetree/bindings/bus/altr,axi-timeout-bridge-1.0.yaml
under the examples section, the timeout-bridge@10000 node places
#address-cells and #size-cells before reg, and interrupts before ranges.

Per Documentation/devicetree/bindings/dts-coding-style.rst and
check_property_order() in scripts/dtc/dt-check-style, properties in a node
are expected to begin with compatible, reg, and ranges, followed by common
properties sorted by their #-stripped names (#address-cells, interrupts,
#size-cells). Running scripts/dtc/dt-check-style --mode=strict on this
binding reports property-order warnings for reg and ranges.

Should the properties in timeout-bridge@10000 be reordered so that
compatible, reg, and ranges come first?

> +
> +        timeout-device@100 {
> +            compatible = "timeout-device";
> +            reg = <0x100 0x10>;
> +        };
> +    };

[Severity: Low]
In Documentation/devicetree/bindings/bus/altr,axi-timeout-bridge-1.0.yaml
under the examples section, the child node timeout-device@100 uses
compatible = "timeout-device", which has no vendor prefix and is not
documented by any binding schema under Documentation/devicetree/bindings/.

When make dt_binding_check runs without DT_SCHEMA_FILES set,
scripts/Makefile.dtbs invokes dt-validate with -m:

    DT_CHECKER ?= dt-validate
    DT_CHECKER_FLAGS ?= $(if $(DT_SCHEMA_FILES),-l $(DT_SCHEMA_FILES),-m)

This checks that every node with a compatible string in the compiled example
matches a known schema, causing validation of
/example-0/timeout-bridge@10000/timeout-device@100 to fail with:

    failed to match any schema with compatible: ['timeout-device']

Could timeout-device@100 in the example use an existing documented
compatible string so that make dt_binding_check passes when dt-validate runs
with -m?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261021-feature-timeout-ip-v2-0-a037be089518@bruker.com?part=1

  reply	other threads:[~2026-10-21 20:05 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-21 19:56 [PATCH v2 0/2] Add Altera timeout bridge driver Vyacheslav Yurkov
2026-10-21 19:56 ` Vyacheslav Yurkov via B4 Relay
2026-10-21 19:56 ` [PATCH v2 1/2] dt-bindings: bus: Add Altera AXI Timeout Bridge Vyacheslav Yurkov
2026-10-21 19:56   ` Vyacheslav Yurkov via B4 Relay
2026-10-21 20:05   ` sashiko-bot [this message]
2026-10-22  2:29   ` Rob Herring (Arm)
2026-10-21 19:56 ` [PATCH v2 2/2] bus: Add Altera AXI Timeout Bridge driver Vyacheslav Yurkov
2026-10-21 19:56   ` Vyacheslav Yurkov via B4 Relay
2026-10-21 20:11   ` sashiko-bot

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