Re: [PATCH v11 1/2] crypto: qce - Only register algos if the user really wants it

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] crypto: qce: missing kernel-parameters.txt doc for do_register_algos
--

commit 47675c12b3c6637f5e62afe90e1fb4f153328b57
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

crypto: qce - Only register algos if the user really wants it

This commit adds a do_register_algos module parameter to the QCE crypto
driver so that crypto algorithms are not registered by default during
probe unless explicitly enabled by the user.

> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index bf3c1bc3ba7bd..5b1bf7a50f88c 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c

[ ... ]

> @@ -22,6 +23,9 @@
>  #include "sha.h"
>  #include "aead.h"
>  
> +static bool do_register_algos;
> +module_param(do_register_algos, bool, 0444);

[Severity: Low]
In drivers/crypto/qce/core.c, module_param(do_register_algos, bool, 0444)
exposes qcrypto.do_register_algos as a kernel command-line and module
parameter to gate devm_qce_register_algs(qce) in qce_crypto_probe().

Should Documentation/admin-guide/kernel-parameters.txt also be updated to
document qcrypto.do_register_algos, along with a parameter description in
drivers/crypto/qce/core.c?

> +
>  #define QCE_QUEUE_LENGTH	1
>  
>  #define QCE_DEFAULT_MEM_BANDWIDTH	393600
> @@ -259,9 +263,11 @@ static int qce_crypto_probe(struct platform_device *pdev)
>  	qce->async_req_enqueue = qce_async_request_enqueue;
>  	qce->async_req_done = qce_async_request_done;
>  
> -	ret = devm_qce_register_algs(qce);
> -	if (ret)
> -		return ret;
> +	if (do_register_algos) {
> +		ret = devm_qce_register_algs(qce);
> +		if (ret)
> +			return ret;
> +	}
>  
>  	/* Configure autosuspend after successful init */
>  	pm_runtime_set_autosuspend_delay(dev, 100);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022-qce-fixes-broken-label-v11-0-0d33c34fd0c3@oss.qualcomm.com?part=1