Re: [PATCH v3 04/10] tools arch x86: Sync the cpufeatures.h copy with the kernel sources

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] tools arch x86: cpufeatures.h out of sync due to unmerged commit 87db7795cbaa
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commit 473988ac3b0546cf1a165c42132612c34c2cdad9
Author: Arnaldo Carvalho de Melo <acme@redhat.com>

tools arch x86: Sync the cpufeatures.h copy with the kernel sources

This commit updates tools/arch/x86/include/asm/cpufeatures.h with new CPU
feature and bug definitions to keep it in sync with the kernel header and
silence the perf build header check warning.

> diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
> index 6547c0aee45b7..fe84cf4e97d35 100644
> --- a/tools/arch/x86/include/asm/cpufeatures.h
> +++ b/tools/arch/x86/include/asm/cpufeatures.h

[ ... ]

> @@ -465,6 +477,8 @@
>  #define X86_FEATURE_NO_NESTED_DATA_BP	(20*32+ 0) /* No Nested Data Breakpoints */
>  #define X86_FEATURE_WRMSR_XX_BASE_NS	(20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing */
>  #define X86_FEATURE_LFENCE_RDTSC	(20*32+ 2) /* LFENCE always serializing / synchronizes RDTSC */
> +
> +#define X86_FEATURE_TLBSYNC_SFW_NO	(20*32+ 4) /* TLBI Erratum #1718 fixed in microcode */
>  #define X86_FEATURE_VERW_CLEAR		(20*32+ 5) /* The memory form of VERW mitigates TSA */
>  #define X86_FEATURE_NULL_SEL_CLR_BASE	(20*32+ 6) /* Null Selector Clears Base */
>  
> @@ -575,4 +589,5 @@
>  #define X86_BUG_TSA			X86_BUG( 1*32+ 9) /* "tsa" CPU is affected by Transient Scheduler Attacks */
>  #define X86_BUG_VMSCAPE			X86_BUG( 1*32+10) /* "vmscape" CPU is affected by VMSCAPE attacks from guests */
>  #define X86_BUG_SEAMRET_INVD_VMCS	X86_BUG( 1*32+11) /* "seamret_invd_vmcs" SEAMRET from P-SEAMLDR clears the current VMCS */
> +#define X86_BUG_TLBI			X86_BUG( 1*32+12) /* "tlbi" AMD TLBI Erratum #1718 */
>  #endif /* _ASM_X86_CPUFEATURES_H */

[Severity: Low]
This patch adds X86_FEATURE_TLBSYNC_SFW_NO and X86_BUG_TLBI to
tools/arch/x86/include/asm/cpufeatures.h to pick up the changes from commit
87db7795cbaa ("x86/CPU/AMD: Fix AMD TLBI Erratum #1718").

However, commit 87db7795cbaa is not present in this tree, so
arch/x86/include/asm/cpufeatures.h does not contain those definitions:

arch/x86/include/asm/cpufeatures.h:
    #define X86_FEATURE_LFENCE_RDTSC	(20*32+ 2) /* LFENCE always serializing / synchronizes RDTSC */
    #define X86_FEATURE_VERW_CLEAR		(20*32+ 5) /* The memory form of VERW mitigates TSA */
    ...
    #define X86_BUG_VMSCAPE			X86_BUG( 1*32+10) /* "vmscape" CPU is affected by VMSCAPE attacks from guests */
    #define X86_BUG_SEAMRET_INVD_VMCS	X86_BUG( 1*32+11) /* "seamret_invd_vmcs" SEAMRET from P-SEAMLDR clears the current VMCS */
    #endif /* _ASM_X86_CPUFEATURES_H */

When building perf, tools/perf/check-headers.sh compares
tools/arch/x86/include/asm/cpufeatures.h against
arch/x86/include/asm/cpufeatures.h and will continue to emit the header
difference warning.

Should the X86_FEATURE_TLBSYNC_SFW_NO and X86_BUG_TLBI additions be dropped
until commit 87db7795cbaa is merged into this branch?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022182431.25673-1-acme@kernel.org?part=4