Re: [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe: unsteered MCR read of GAMCTRL PF queue registers in devcoredump
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commit 1da764eb534ebe0a6ed34a1262b84f79a5f87633
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>

drm/xe: dump GAM page fault report registers in devcoredump

This commit adds definitions for PAGE_FLTRPTQ_HEAD_GAMCTRL and
PAGE_FLTRPTQ_TAIL_GAMCTRL and captures them during devcoredump snapshots.
It also prints the captured values in the devcoredump output along with a
page fault notice when the head and tail registers differ.

> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index e93895e0c731a..e9eb0bd04af10 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -530,6 +530,9 @@
>  #define   LMEM_EN				REG_BIT(31)
>  #define   LMTT_DIR_PTR				REG_GENMASK(30, 0) /* in multiples of 64KB */
>  
> +#define PAGE_FLTRPTQ_HEAD_GAMCTRL		XE_REG(0xcf90)
> +#define PAGE_FLTRPTQ_TAIL_GAMCTRL		XE_REG(0xcf94)
> +
>  #define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
>  #define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
>  
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> index 49a7c020a1615..8d59f80e2929f 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
> @@ -114,6 +114,11 @@ static const struct xe_reg_desc xe_dbg_media_gt_rpm_reglist[] = {
>  	XE_REG_DESC(RPM_GCD, "RPM_GCD"),
>  };
>  
> +static const struct xe_reg_desc xe_dbg_gam_pf_reglist[] = {
> +	XE_REG_DESC(PAGE_FLTRPTQ_HEAD_GAMCTRL, "PAGE_FLTRPTQ_HEAD_GAMCTRL"),
> +	XE_REG_DESC(PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"),
> +};

[Severity: Medium]
Should PAGE_FLTRPTQ_HEAD_GAMCTRL (0xcf90) and PAGE_FLTRPTQ_TAIL_GAMCTRL
(0xcf94) be defined as MCR registers with XE_REG_MCR() and captured via
steered MCR reads instead of raw xe_mmio_read32()?

In drivers/gpu/drm/xe/xe_gt_mcr.c, the 0x00C800 to 0x00CFFF GAM/GAMCTRL
range is listed in the INSTANCE0 steering tables across Xe platforms (such
as xehpc_instance0_steering_table, xelpg_instance0_steering_table,
xe2lpg_instance0_steering_table, xe3p_lpg_instance0_steering_table, and
xe3p_xpc_instance0_steering_table):

drivers/gpu/drm/xe/xe_gt_mcr.c:
	{ 0x00C800, 0x00CFFF },		/* GAMCTRL */

Because rw_with_mcr_steering() leaves the last-used group and instance
programmed in MCR_SELECTOR / MTL_MCR_SELECTOR (and on GRAPHICS_VERx100(xe)
>= 1270, MTL_MCR_SELECTOR is shared with GuC and serialized via
gt->mcr_lock and STEER_SEMAPHORE), reading these registers in
devcoredump_snapshot() -> xe_devcoredump_capture_gt_regs() ->
xe_dbg_gt_snapshot_capture() -> xe_dbg_reg_snapshot_capture_target() via
unsteered xe_mmio_read32() can race with concurrent MCR steering or target
a terminated non-(0, 0) GAMCTRL instance. When that happens, both reads
return 0x00000000 and xe_gam_pf_snapshot_print() will not print the page
fault message even if a fault occurred.

Even with the subsequent patch in the series ("drm/xe: capture L3 node
status registers in devcoredump") adding XE_REG_DESC_MCR() and updating
xe_dbg_reg_snapshot_capture_target() to call xe_gt_mcr_unicast_read_any()
for MCR descriptors, PAGE_FLTRPTQ_HEAD_GAMCTRL and
PAGE_FLTRPTQ_TAIL_GAMCTRL remain defined with XE_REG() and XE_REG_DESC(),
so they still bypass xe_gt_mcr_unicast_read_any().

Additionally, on Xe3p+ platforms where xe_guc_using_main_gamctrl_queues()
is true (GT_VER(gt) >= 35), xe_guc_upload() switches hardware and GuC to
the unicast Main GAMCTRL queues:

drivers/gpu/drm/xe/xe_guc.c:xe_guc_upload() {
	if (xe_guc_using_main_gamctrl_queues(guc))
		xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
}

On those platforms, are 0xcf90 and 0xcf94 still the active page fault
reporting queue registers to capture in xe_devcoredump_capture_gt_regs()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261023060554.2643515-1-naresh.kumar.g@intel.com?part=4