Re: [PATCH 2/2] serial: 8250_ingenic: Start the X1600 UART from 16 clocks a bit

[sashiko-bot@kernel.org]

> The X1600 UART samples each bit with UMR clocks, adjusted per bit by
> UACR, while the divisor the 8250 core computes assumes 16. The driver
> never sets them, so the UART keeps what ran before it: on a HiBy R1 the
> vendor kernel leaves UART0's UMR at 8, which by the register's meaning
> doubles every rate set here (the line rate itself was not measured). The
> Bluetooth chip on that UART then never answers: "command 0xfc18 tx
> timeout" from hci_bcm.
> 
> Add an X1600 entry that writes UMR = 16 and UACR = 0 at probe. The
> offsets come from Rockbox's X1600 register headers and match the UMR
> read on the R1. The X1000, whose compatible the X1600's falls back to,
> may have the same registers, but I could not check one, so it is left
> alone.
> 
> Tested on a HiBy R1: UMR reads 16 and UACR 0 after probe, and the
> BCM43430A1 on UART0 comes up at 1.5 Mbaud and streams A2DP audio.
> 
> Signed-off-by: Olivier Louvignes <olivier@mgcrea.io>

Sashiko has reviewed this patch and found no issues.

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Sashiko AI review · https://sashiko.dev/#/patchset/20261024051515.55639-1-olivier@mgcrea.io?part=2