Re: [PATCH v2 3/3] arm64: dts: allwinner: a523: drop the PA GPIO interrupt

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] pinctrl: sunxi: sunxi_irq_base_reg() ignores irq_bank_map on A733
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commit 1d99efa95c547fd409284e1974176bcf35345f69
Author: Pablo Mazzini <pmazzini@gmail.com>

pinctrl: sunxi: dt: number the IRQ banks from the first one that has IRQs

This commit updates prepare_function_table() in the sunxi DT pinctrl
driver to number logical IRQ banks starting from 0 at the first bank that
supports interrupts, rather than starting from PA. It also updates
a523_irq_bank_map and adds a733_irq_bank_map to map logical IRQ banks
0..9 back to hardware banks 1..10 (PB..PK).

> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c
> index ca82f08a3a65b..3ebe926a1bc6b 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c
> @@ -21,8 +21,11 @@ static const u8 a733_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
>  /*	  PA  PB  PC  PD  PE  PF  PG  PH  PI  PJ  PK */
>  	{  0, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14};
>  
> +static const unsigned int a733_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
> +
>  static struct sunxi_pinctrl_desc a733_pinctrl_data = {
> -	.irq_banks = 10,
> +	.irq_banks = ARRAY_SIZE(a733_irq_bank_map),
> +	.irq_bank_map = a733_irq_bank_map,
>  	.irq_read_needs_mux = true,
>  	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
>  };

[Severity: High]
Does sunxi_irq_base_reg() in drivers/pinctrl/sunxi/pinctrl-sunxi.h ignore
a733_irq_bank_map when SUNXI_PINCTRL_NCAT3_REG_LAYOUT is set?

In drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c, a733_pinctrl_probe() passes
SUNXI_PINCTRL_NCAT3_REG_LAYOUT to sunxi_pinctrl_dt_table_init(). However,
when accessing IRQ registers via sunxi_irq_cfg_reg(), sunxi_irq_ctrl_reg(),
sunxi_irq_status_reg(), or sunxi_irq_debounce_reg(), sunxi_irq_base_reg()
only calls sunxi_irq_hw_bank_num() on the non-NCAT3 path:

drivers/pinctrl/sunxi/pinctrl-sunxi.h:sunxi_irq_base_reg() {
	if (pctl->flags & SUNXI_PINCTRL_NCAT3_REG_LAYOUT)
		return pctl->bank_offset + bank * pctl->bank_mem_size +
		       A733_IRQ_REGS_OFFSET;

	return IRQ_REGS_OFFSET +
	       sunxi_irq_hw_bank_num(pctl->desc, bank) * IRQ_MEM_SIZE;
}

With prepare_function_table() in drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c
now numbering PB..PK as logical IRQ banks 0..9 instead of 1..10, and
pctl->bank_offset set to A733_BANK_OFFSET (0x80, the base of PA),
passing the unmapped bank index in the SUNXI_PINCTRL_NCAT3_REG_LAYOUT
branch shifts every GPIO IRQ register access on the A733 down by one bank
(0x80 bytes), so PB..PK access offsets 0x0c0..0x540 (PA..PJ) instead of
0x140..0x5c0.

Should the SUNXI_PINCTRL_NCAT3_REG_LAYOUT branch in sunxi_irq_base_reg()
also translate bank through sunxi_irq_hw_bank_num(pctl->desc, bank)?

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Sashiko AI review · https://sashiko.dev/#/patchset/20261025135745.102970-1-pmazzini@gmail.com?part=3