From: sashiko-bot@kernel.org
To: "Michael Kelley" <mhkelley58@gmail.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 1/1] PCI: hv: Spread load across CPUs when selecting effective affinity CPU
Date: Mon, 26 Oct 2026 08:58:00 +0000 [thread overview]
Message-ID: <sashiko-outbox-184713@kernel.org> (raw)
In-Reply-To: <20261026045930.129874-1-mhklinux@outlook.com>
> In a system with multiple devices with the same configuration (such as
> NVMe controllers), the affinity masks are the same for all such devices.
> Linux typicaly must select a single CPU from each mask to be the effective
> affinity. If a fixed algorithm is used, such as picking the first CPU
> in the mask, interrupts from multiple devices are assigned to the same
> CPUs, while other CPUs are not assigned any interrupts, producing an
> interrupt load imbalance.
>
> On x86, the "APIC" IRQ chip avoids this problem by spreading the
> interrupts across the CPUs in an affinity mask. It tracks the number
> of IRQs assigned to each CPU, and chooses the CPU in the mask that
> has the fewest assignments. Because Hyper-V vPCI device IRQs eventually
> parent to APIC, the spreading done by APIC accrues to Hyper-V vPCI
> devices, so all is good in x86 systems.
>
> [ ... ]
> IRQ chip (GICv3) to actually set that single CPU as the effective
> affinity in the virtual GICv3 hardware. As a result, IRQs are spread
> across CPUs like on x86 and interrupt load imbalances are avoided.
>
> Signed-off-by: Michael Kelley <mhklinux@outlook.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261026045930.129874-1-mhklinux@outlook.com?part=1
prev parent reply other threads:[~2026-10-26 8:58 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 4:59 [PATCH v2 1/1] PCI: hv: Spread load across CPUs when selecting effective affinity CPU Michael Kelley
2026-10-26 8:55 ` Naman Jain
2026-10-26 15:59 ` Michael Kelley
2026-10-26 8:58 ` sashiko-bot [this message]
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