Re: [PATCH 9/9] arm64: dts: airoha: en7581: add integrated switch node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] arm64: dts: airoha: missing interrupts property on en7581 internal switch PHYs
- [Low] arm64: dts: airoha: invalid #address-cells/#size-cells on en7581 switch node
- [Low] arm64: dts: airoha: misplaced phy-mode property on en7581 ethernet-phy nodes
--

commit f50b3495d44d1f59372ccf1eb2beb38da392948c
Author: Christian Marangi <ansuelsmth@gmail.com>

arm64: dts: airoha: en7581: add integrated switch node

This patch adds the integrated switch node for the Airoha EN7581 SoC,
including its ports, internal MDIO bus, internal PHY nodes, and PHY LED
subnodes.

> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> index f214fa3a3e2bb..83ae41271f96f 100644
> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> @@ -4,6 +4,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/clock/en7523-clk.h>
>  #include <dt-bindings/reset/airoha,en7581-reset.h>
> +#include <dt-bindings/leds/common.h>
>  #include <dt-bindings/thermal/thermal.h>
>  
>  / {
> @@ -470,6 +471,152 @@ fixed-link {
>  			};
>  		};
>  
> +		switch: switch@1fb58000 {
> +			compatible = "airoha,en7581-switch";
> +			reg = <0 0x1fb58000 0 0x8000>;
> +			resets = <&scuclk EN7581_GSW_RST>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +
> +			#address-cells = <1>;
> +			#size-cells = <1>;

[Severity: Low]
Should #address-cells and #size-cells be dropped from switch@1fb58000?

The binding schema in
Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml sets
unevaluatedProperties: false and only allows #address-cells and #size-cells
inside the ports and mdio child nodes, not on the top-level switch node.

In addition, because switch@1fb58000 has no ranges or dma-ranges property and
its direct children (ports and mdio) do not use reg or ranges,
check_avoid_unnecessary_addr_size() in scripts/dtc/checks.c warns about
unnecessary #address-cells/#size-cells when building with W=1.

> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				gsw_port1: port@1 {
> +					reg = <1>;
> +					phy-mode = "internal";
> +					phy-handle = <&gsw_phy1>;
> +				};

[ ... ]

> +			mdio: mdio {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				gsw_phy1: ethernet-phy@9 {
> +					compatible = "ethernet-phy-ieee802.3-c22";
> +					reg = <9>;

[Severity: Medium]
Are gsw_phy1 through gsw_phy4 missing interrupts properties referencing the
switch interrupt controller?

Above, switch@1fb58000 is configured as an interrupt-controller wired to
GIC_SPI 31, and mt7530_setup_irq() registers the switch regmap_irq_chip
domain. However, in drivers/net/dsa/mt7530.c:mt7530_setup_mdio():

	if (priv->irq_domain && !mnp)
		mt7530_setup_mdio_irq(priv);

	ret = devm_of_mdiobus_register(dev, bus, mnp);

when an explicit mdio child node (mnp) is present in the device tree,
mt7530_setup_mdio_irq() is skipped (and only covers PHY addresses 0..4 in any
case). Instead, devm_of_mdiobus_register() calls
fwnode_mdiobus_phy_device_register() -> fwnode_irq_get(child, 0) on each
ethernet-phy node.

Without interrupts properties on gsw_phy1, gsw_phy2, gsw_phy3, and gsw_phy4,
fwnode_irq_get() fails and all four internal PHYs fall back to PHY_POLL
instead of using the switch's link-change interrupts.

> +					phy-mode = "internal";

[Severity: Low]
Is phy-mode = "internal" intended on the ethernet-phy@9 through
ethernet-phy@c nodes (gsw_phy1..gsw_phy4)?

The phy-mode property is a MAC/DSA port property defined in
Documentation/devicetree/bindings/net/ethernet-controller.yaml and is already
present on the corresponding switch port nodes gsw_port1..gsw_port4, whereas
Documentation/devicetree/bindings/net/ethernet-phy.yaml does not define
phy-mode on PHY nodes.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026095727.31708-1-ansuelsmth@gmail.com?part=9