Re: [PATCH] PCI/PM: Serialize PMCSR updates against PME handling

[sashiko-bot@kernel.org]

> PME handling and native power transitions independently read and update
> PMCSR. Config access locking protects individual transactions, so a PME
> worker can read D0, another CPU can request D3hot, and the worker can write
> its stale D0 state back while acknowledging PME status. This was observed
> during normal runtime PM of an NVIDIA UCSI controller, followed by a
> D0-to-D3hot refusal message.
> 
> Serialize native PCI-core PMCSR writers with the existing capability
> lock, releasing it before transition delays and readiness waits.
> State-only updates write zero to the RW1C PME_Status bit to preserve
> pending wakeups. Read fresh PMCSR for each PM-reset transition instead of
> keeping a stale word across the cooldown. Keep the literal-zero power-up
> write.
> 
> Fixes: 58ff463396ad ("PCI PM: Add function for checking PME status of devices")
> Signed-off-by: Giuseppe Piscitelli <ooonea@gmail.com>

Sashiko has reviewed this patch and found no issues.

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