From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793201778; b=x8Tl2ytXe51PF6L5p6mq2ksdnJL3cJbctb2eQf7X8/LpMtZDS6ReMChtssrLqVIqTaO9 H+XOAEA5nuLqjxrqf+ea1ejNFa+HqS8Q1tiZBMwYwc401l+P1R8/TI1odUWq2RtsfN2zd TCo7a8AiLD80R2QVBV+EeET8CHIl07eF6i4y35g/B8kFeFVb8oGD4fOwgfcxEXj9KbKjJ xA2MM5Rk/K6v5+wT18s8QuYukYmllqmVENE12VjyFaGOIpxVsIbLpRfXJwwBUQa3L7tI9 wekZqJFPYX+Nr8BM3nmhKMm9QPlpVPDpK7ArqAFcT42J4MV7TVwGjkgO4WPnKUMwdgg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793201778; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=NcBMAsscOX++K8Pwqm1G7DDSp4gQMpAWt2lAFd4UW3U=; b=ppJrjRWb1zbVmUktReEJAYUF1iePEjOQQq5wdCY+9yw63lqIBpVLAjRGki3TMHnHAHfn 79utfN6gnvqo/LhqmuR+9S9PYSPwmbO/h2IhF/EiP88JCoKn+oHNf1wA8Q1ZQVhBUyhga 6FwXSOrmd3QrwdowH63wRkBoQC6xebAb0jnk4KqLhYsJTIj+WSpCtiEUbfybMN3q0QT66 0wFEf3LWr6HkK7f6heV79y24CIKfwHz7kzJQeRb0zl23VIxI/bcNOOJTFIv+no+Tnz9u2 ElEKIEp2k1iV8oiOwNalHEJvBkv0Wudrkau5sXm1AVGOBaXf/VibOp7XjWERntayvgg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b="ENS9tKz/"; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEF8960A2604 for ; Wed, 28 Oct 2026 15:36:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=ENS9tKz/ Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4A14D1F01242; Wed, 28 Oct 2026 15:36:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793201777; bh=NcBMAsscOX++K8Pwqm1G7DDSp4gQMpAWt2lAFd4UW3U=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=ENS9tKz/j5zjSyLFESyOhELFO/mfE2g7oUwFcvJAANP9VQCBp5Lzz9xozhTOymmAS ywBrDUq8hEIxjJcy2oWiem72saWgu0XFUvzRh4eQEz/WSynXNRwqbu0AL0uLuG7k5d mJRmk+p9gn+nGxZt4KR7j0xrNis4WONi7IccBrP/Ia5rhR6M12vnaDWLjYOjeyewCI oIQTuoa1D+vvtY+ZfOxY+i/npzjeO1yTVCdiiF8qctzsYz6Fr9BA7C87u4Hp0ZwCm/ z441abUJbh1OdHqlzTo1DGU8xW9ULPlQHe4ttqHNiHIl/8fTKVBuywlVWjCFntM2US bvx8AiUKSuDVg== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v23 09/15] media: qcom: camss: csid: Add support for CSID 1080 Reply-To: sashiko-reviews@lists.linux.dev To: "Hangxiang Ma" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, media-ci@linuxtv.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261028-kaanapali-camss-v23-9-95f250b18612@oss.qualcomm.com> References: <20261028-kaanapali-camss-v23-0-95f250b18612@oss.qualcomm.com> <20261028-kaanapali-camss-v23-9-95f250b18612@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Wed, 28 Oct 2026 15:36:16 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 3 potential issue(= s) to consider: - [High] media: qcom: camss: out-of-bounds fmt access in __csid_configure_r= di_stream() - [Medium] media: qcom: camss: csid-1080: race on addr_update and reg_updat= e bitmasks - [Low] media: qcom: camss: unused variable lane_cnt in __csid_configure_rd= i_stream() -- commit a4bf52311267182465594dfcec0df1e6e7980755 Author: Hangxiang Ma media: qcom: camss: csid: Add support for CSID 1080 This commit adds hardware resource definitions and driver support for the CSID 1080 module on the Qualcomm Kaanapali SoC, including RUP/AUP register update handling, stream configuration, reset, and BUF_DONE interrupt handling. > diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.c b/driver= s/media/platform/qcom/camss/camss-csid-1080.c > new file mode 100644 > index 0000000000000..3d90d31201fa5 > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-csid-1080.c [ ... ] > +#define MSM_CSID_MAX_SRC_STREAMS_1080 (csid_is_lite(csid) ? 4 : 5) [ ... ] > +static void __csid_addr_update(struct csid_device *csid, int port_id) > +{ > + csid->addr_update |=3D CSID_RUP_AUP_RDI(port_id); > + writel(csid->addr_update, csid->base + CSID_AUP_CMD); > + > + __csid_aup_rup_trigger(csid); > +} > + > +static void __csid_addr_update_clear(struct csid_device *csid, int port_= id) > +{ > + csid->addr_update &=3D ~CSID_RUP_AUP_RDI(port_id); > +} > + > +static void __csid_reg_update(struct csid_device *csid, int port_id) > +{ > + csid->reg_update |=3D CSID_RUP_AUP_RDI(port_id); > + writel(csid->reg_update, csid->base + CSID_RUP_CMD); > + > + __csid_aup_rup_trigger(csid); > +} > + > +static void __csid_reg_update_clear(struct csid_device *csid, int port_i= d) > +{ > + csid->reg_update &=3D ~CSID_RUP_AUP_RDI(port_id); > +} [ ... ] > +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 ena= ble, u8 port, u8 vc) > +{ > + u8 lane_cnt =3D csid->phy.lane_cnt; > + u32 val; > + > + /* Source pads matching RDI channels on hardware. > + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. > + */ > + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIR= ST_SRC + port]; > + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res-= >formats->formats, > + csid->res->formats->nformats, > + input_format->code); > + > + if (!lane_cnt) > + lane_cnt =3D 4; [Severity: Low] In __csid_configure_rdi_stream(), lane_cnt is initialized and updated here but never read anywhere in the function. Will this trigger an -Wunused-but-set-variable warning? > + > + val =3D RDI_CFG0_TIMESTAMP_EN; > + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; > + val |=3D RDI_CFG0_RETIME_BS; > + > + /* note: for non-RDI path, this should be format->decode_format */ > + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; > + val |=3D vc << RDI_CFG0_VC; > + val |=3D format->data_type << RDI_CFG0_DT; > + writel(val, csid->base + CSID_RDI_CFG0(port)); > + > + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; > + writel(val, csid->base + CSID_RDI_CFG1(port)); > + > + /* Configure pixel store using dedicated register in 1080 */ > + if (!csid_is_lite(csid)) > + __csid_configure_rdi_pix_store(csid, port); > + > + val =3D 0; > + writel(val, csid->base + CSID_RDI_CTRL(port)); > + > + val =3D readl(csid->base + CSID_RDI_CFG0(port)); > + > + if (enable) > + val |=3D RDI_CFG0_EN; > + > + writel(val, csid->base + CSID_RDI_CFG0(port)); > +} > + > +static void csid_configure_stream(struct csid_device *csid, u8 enable) > +{ > + u8 i, k; > + > + __csid_configure_rx(csid, &csid->phy); > + > + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + __csid_configure_rdi_stream(csid, enable, i, 0); [Severity: High] Can this read past the end of csid->fmt[] on non-lite CSID 1080 instances? For non-lite instances (CSID0, CSID1, CSID2 in csid_res_kaanapali), MSM_CSID_MAX_SRC_STREAMS_1080 evaluates to 5, so csid_configure_stream() iterates i from 0 to 4 and passes port =3D 4 into __csid_configure_rdi_stream(). Inside __csid_configure_rdi_stream(), input_format is computed as: struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST_= SRC + port]; However, in drivers/media/platform/qcom/camss/camss-csid.h, MSM_CSID_PAD_FIRST_SRC is 1 and MSM_CSID_PADS_NUM is still 5: #define MSM_CSID_PAD_SINK 0 #define MSM_CSID_PAD_FIRST_SRC 1 #define MSM_CSID_PADS_NUM 5 ... struct csid_device { ... struct media_pad pads[MSM_CSID_PADS_NUM]; ... struct v4l2_mbus_framefmt fmt[MSM_CSID_PADS_NUM]; When port is 4, MSM_CSID_PAD_FIRST_SRC + port is 5, which indexes one element past the end of csid->fmt[5] when reading input_format->code (and msm_csid_register_entity() only registers 4 source pads). Should MSM_CSID_PADS_NUM and MSM_CSID_MAX_SRC_STREAMS be updated to accommodate the 5th RDI stream, or should MSM_CSID_MAX_SRC_STREAMS_1080 be capped to the number of source pads? > + __csid_configure_rx_vc(csid, 0); > + > + for (k =3D 0; k < CAMSS_INIT_BUF_COUNT; k++) > + __csid_addr_update(csid, i); > + > + __csid_reg_update(csid, i); > + > + __csid_ctrl_rdi(csid, enable, i); > + } > + } > +} [ ... ] > +static irqreturn_t csid_isr(int irq, void *dev) > +{ > + struct csid_device *csid =3D dev; > + u32 val, buf_done_val; > + u8 reset_done; > + int i; > + > + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); > + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); > + > + reset_done =3D val & INFO_RST_DONE; > + > + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); > + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); > + > + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); > + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); > + > + if (val & INFO_RUP_DONE) { > + __csid_addr_update_clear(csid, i); > + __csid_reg_update_clear(csid, i); > + } > + > + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) > + camss_buf_done(csid->camss, csid->id, i); [Severity: Medium] Could the unlocked updates to csid->addr_update and csid->reg_update here race with vfe_queue_buffer_v2() and vfe_enable_output_v2(), or re-trigger updates for other RDI ports? In drivers/media/platform/qcom/camss/camss-vfe.c, vfe_queue_buffer_v2() and vfe_enable_output_v2() call ops->addr_update() and ops->reg_update() while holding vfe->output_lock: vfe_queue_buffer_v2() spin_lock_irqsave(&vfe->output_lock, flags); ops->addr_update(vfe, line->id) -> csid_subdev_addr_update() -> __csid_addr_update() ops->reg_update(vfe, line->id) -> csid_subdev_reg_update() -> __csid_reg_update() In csid_isr(), __csid_addr_update_clear() and __csid_reg_update_clear() modify csid->addr_update and csid->reg_update without holding vfe->output_lock or a CSID spinlock. If csid_isr() runs on one CPU while vfe_queue_buffer_v2() or vfe_enable_output_v2() runs on another CPU, the read-modify-write on csid->addr_update and csid->reg_update can lose a newly set RDI bit or write a stale cleared bit back into CSID_AUP_CMD and CSID_RUP_CMD. Also, within this loop in csid_isr(), camss_buf_done() -> vfe_buf_done() is called for port i before INFO_RUP_DONE is checked and cleared for ports j > i. When vfe_buf_done() calls __csid_addr_update(csid, i), it writes the entire csid->addr_update bitmask to CSID_AUP_CMD while completed ports j > i still have their CSID_RUP_AUP_RDI(j) bits set. Should INFO_RUP_DONE be processed for all ports before invoking camss_buf_done(), or does CSID_AUP_CMD / CSID_RUP_CMD only need CSID_RUP_AUP_RDI(port_id) written directly? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261028-kaanapali-= camss-v23-0-95f250b18612@oss.qualcomm.com?part=3D9 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CC1960A262E for ; Wed, 28 Oct 2026 15:36:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=hZFM8pS1; dkim=fail reason="signature verification failed" (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=ENS9tKz/ DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Date:References: In-Reply-To:Cc:To:Subject:From:Message-ID:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Unsubscribe-Post:List-Owner; bh=ovJ/D0qerdIgJticL6xMxxBK8o52iX1gmnhIYxDpd38=; b=hZFM8pS1/r3/7KccXDIAWSVj1M Y4jyPcT2bDeNBCWxR/Tb5FOzus+CGVnoQ/QbmxAWHZPb7jOvVL7L3prizF/Ux+e4sZf98eKhAHMDN nSn4XatbMw4+GZSPUtURjS0vQqKODMURSjESw0MWjFEED82FXa/o++bgS8w3R/g525Pnj2vzKee5E Z5+ZVvnAe/DflQnFQ+3cJd7CkMsvHCPzkadAAI+o2aHcN7heLSV+ICVVud9hz/VBOU/YYSJTl4BmD iwj6Zk9ffBtwkmwS77DwYEbyt2Ai/qiibwNKIy/ZwYheCP2Fgufpy45csZnf9bBXVTkf0u36Aq72o bxgOOq/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xM5hM-00000007Phw-3lBn; Wed, 28 Oct 2026 15:36:20 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xM5hL-00000007PhJ-026O for linux-phy@lists.infradead.org; Wed, 28 Oct 2026 15:36:19 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id F352343E13; Wed, 28 Oct 2026 15:36:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4A14D1F01242; Wed, 28 Oct 2026 15:36:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793201777; bh=NcBMAsscOX++K8Pwqm1G7DDSp4gQMpAWt2lAFd4UW3U=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=ENS9tKz/j5zjSyLFESyOhELFO/mfE2g7oUwFcvJAANP9VQCBp5Lzz9xozhTOymmAS ywBrDUq8hEIxjJcy2oWiem72saWgu0XFUvzRh4eQEz/WSynXNRwqbu0AL0uLuG7k5d mJRmk+p9gn+nGxZt4KR7j0xrNis4WONi7IccBrP/Ia5rhR6M12vnaDWLjYOjeyewCI oIQTuoa1D+vvtY+ZfOxY+i/npzjeO1yTVCdiiF8qctzsYz6Fr9BA7C87u4Hp0ZwCm/ z441abUJbh1OdHqlzTo1DGU8xW9ULPlQHe4ttqHNiHIl/8fTKVBuywlVWjCFntM2US bvx8AiUKSuDVg== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v23 09/15] media: qcom: camss: csid: Add support for CSID 1080 To: "Hangxiang Ma" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, media-ci@linuxtv.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261028-kaanapali-camss-v23-9-95f250b18612@oss.qualcomm.com> References: <20261028-kaanapali-camss-v23-0-95f250b18612@oss.qualcomm.com> <20261028-kaanapali-camss-v23-9-95f250b18612@oss.qualcomm.com> Date: Wed, 28 Oct 2026 15:36:16 +0000 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MyBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIG1lZGlhOiBxY29tOiBj YW1zczogb3V0LW9mLWJvdW5kcyBmbXQgYWNjZXNzIGluIF9fY3NpZF9jb25maWd1cmVfcmRpX3N0 cmVhbSgpCi0gW01lZGl1bV0gbWVkaWE6IHFjb206IGNhbXNzOiBjc2lkLTEwODA6IHJhY2Ugb24g YWRkcl91cGRhdGUgYW5kIHJlZ191cGRhdGUgYml0bWFza3MKLSBbTG93XSBtZWRpYTogcWNvbTog Y2Ftc3M6IHVudXNlZCB2YXJpYWJsZSBsYW5lX2NudCBpbiBfX2NzaWRfY29uZmlndXJlX3JkaV9z dHJlYW0oKQotLQoKY29tbWl0IGE0YmY1MjMxMTI2NzE4MjQ2NTU5NGRmY2VjMGRmMWU2ZTc5ODA3 NTUKQXV0aG9yOiBIYW5neGlhbmcgTWEgPGhhbmd4aWFuZy5tYUBvc3MucXVhbGNvbW0uY29tPgoK bWVkaWE6IHFjb206IGNhbXNzOiBjc2lkOiBBZGQgc3VwcG9ydCBmb3IgQ1NJRCAxMDgwCgpUaGlz IGNvbW1pdCBhZGRzIGhhcmR3YXJlIHJlc291cmNlIGRlZmluaXRpb25zIGFuZCBkcml2ZXIgc3Vw cG9ydCBmb3IgdGhlCkNTSUQgMTA4MCBtb2R1bGUgb24gdGhlIFF1YWxjb21tIEthYW5hcGFsaSBT b0MsIGluY2x1ZGluZyBSVVAvQVVQIHJlZ2lzdGVyCnVwZGF0ZSBoYW5kbGluZywgc3RyZWFtIGNv bmZpZ3VyYXRpb24sIHJlc2V0LCBhbmQgQlVGX0RPTkUgaW50ZXJydXB0CmhhbmRsaW5nLgoKPiBk aWZmIC0tZ2l0IGEvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNzLWNzaWQt MTA4MC5jIGIvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNzLWNzaWQtMTA4 MC5jCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAwLi4zZDkwZDMx MjAxZmE1Cj4gLS0tIC9kZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0vcWNv bS9jYW1zcy9jYW1zcy1jc2lkLTEwODAuYwoKWyAuLi4gXQoKPiArI2RlZmluZSBNU01fQ1NJRF9N QVhfU1JDX1NUUkVBTVNfMTA4MAkJKGNzaWRfaXNfbGl0ZShjc2lkKSA/IDQgOiA1KQoKWyAuLi4g XQoKPiArc3RhdGljIHZvaWQgX19jc2lkX2FkZHJfdXBkYXRlKHN0cnVjdCBjc2lkX2RldmljZSAq Y3NpZCwgaW50IHBvcnRfaWQpCj4gK3sKPiArCWNzaWQtPmFkZHJfdXBkYXRlIHw9IENTSURfUlVQ X0FVUF9SREkocG9ydF9pZCk7Cj4gKwl3cml0ZWwoY3NpZC0+YWRkcl91cGRhdGUsIGNzaWQtPmJh c2UgKyBDU0lEX0FVUF9DTUQpOwo+ICsKPiArCV9fY3NpZF9hdXBfcnVwX3RyaWdnZXIoY3NpZCk7 Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIF9fY3NpZF9hZGRyX3VwZGF0ZV9jbGVhcihzdHJ1Y3Qg Y3NpZF9kZXZpY2UgKmNzaWQsIGludCBwb3J0X2lkKQo+ICt7Cj4gKwljc2lkLT5hZGRyX3VwZGF0 ZSAmPSB+Q1NJRF9SVVBfQVVQX1JESShwb3J0X2lkKTsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQg X19jc2lkX3JlZ191cGRhdGUoc3RydWN0IGNzaWRfZGV2aWNlICpjc2lkLCBpbnQgcG9ydF9pZCkK PiArewo+ICsJY3NpZC0+cmVnX3VwZGF0ZSB8PSBDU0lEX1JVUF9BVVBfUkRJKHBvcnRfaWQpOwo+ ICsJd3JpdGVsKGNzaWQtPnJlZ191cGRhdGUsIGNzaWQtPmJhc2UgKyBDU0lEX1JVUF9DTUQpOwo+ ICsKPiArCV9fY3NpZF9hdXBfcnVwX3RyaWdnZXIoY3NpZCk7Cj4gK30KPiArCj4gK3N0YXRpYyB2 b2lkIF9fY3NpZF9yZWdfdXBkYXRlX2NsZWFyKHN0cnVjdCBjc2lkX2RldmljZSAqY3NpZCwgaW50 IHBvcnRfaWQpCj4gK3sKPiArCWNzaWQtPnJlZ191cGRhdGUgJj0gfkNTSURfUlVQX0FVUF9SREko cG9ydF9pZCk7Cj4gK30KClsgLi4uIF0KCj4gK3N0YXRpYyB2b2lkIF9fY3NpZF9jb25maWd1cmVf cmRpX3N0cmVhbShzdHJ1Y3QgY3NpZF9kZXZpY2UgKmNzaWQsIHU4IGVuYWJsZSwgdTggcG9ydCwg dTggdmMpCj4gK3sKPiArCXU4IGxhbmVfY250ID0gY3NpZC0+cGh5LmxhbmVfY250Owo+ICsJdTMy IHZhbDsKPiArCj4gKwkvKiBTb3VyY2UgcGFkcyBtYXRjaGluZyBSREkgY2hhbm5lbHMgb24gaGFy ZHdhcmUuCj4gKwkgKiBFLmcuIFBhZCAxIC0+IFJESTAsIFBhZCAyIC0+IFJESTEsIGV0Yy4KPiAr CSAqLwo+ICsJc3RydWN0IHY0bDJfbWJ1c19mcmFtZWZtdCAqaW5wdXRfZm9ybWF0ID0gJmNzaWQt PmZtdFtNU01fQ1NJRF9QQURfRklSU1RfU1JDICsgcG9ydF07Cj4gKwljb25zdCBzdHJ1Y3QgY3Np ZF9mb3JtYXRfaW5mbyAqZm9ybWF0ID0gY3NpZF9nZXRfZm10X2VudHJ5KGNzaWQtPnJlcy0+Zm9y bWF0cy0+Zm9ybWF0cywKPiArCQkJCQkJCQkgICBjc2lkLT5yZXMtPmZvcm1hdHMtPm5mb3JtYXRz LAo+ICsJCQkJCQkJCSAgIGlucHV0X2Zvcm1hdC0+Y29kZSk7Cj4gKwo+ICsJaWYgKCFsYW5lX2Nu dCkKPiArCQlsYW5lX2NudCA9IDQ7CgpbU2V2ZXJpdHk6IExvd10KSW4gX19jc2lkX2NvbmZpZ3Vy ZV9yZGlfc3RyZWFtKCksIGxhbmVfY250IGlzIGluaXRpYWxpemVkIGFuZCB1cGRhdGVkIGhlcmUK YnV0IG5ldmVyIHJlYWQgYW55d2hlcmUgaW4gdGhlIGZ1bmN0aW9uLiBXaWxsIHRoaXMgdHJpZ2dl ciBhbgotV3VudXNlZC1idXQtc2V0LXZhcmlhYmxlIHdhcm5pbmc/Cgo+ICsKPiArCXZhbCA9IFJE SV9DRkcwX1RJTUVTVEFNUF9FTjsKPiArCXZhbCB8PSBSRElfQ0ZHMF9USU1FU1RBTVBfU1RCX1NF TDsKPiArCXZhbCB8PSBSRElfQ0ZHMF9SRVRJTUVfQlM7Cj4gKwo+ICsJLyogbm90ZTogZm9yIG5v bi1SREkgcGF0aCwgdGhpcyBzaG91bGQgYmUgZm9ybWF0LT5kZWNvZGVfZm9ybWF0ICovCj4gKwl2 YWwgfD0gREVDT0RFX0ZPUk1BVF9QQVlMT0FEX09OTFkgPDwgUkRJX0NGRzBfREVDT0RFX0ZPUk1B VDsKPiArCXZhbCB8PSB2YyA8PCBSRElfQ0ZHMF9WQzsKPiArCXZhbCB8PSBmb3JtYXQtPmRhdGFf dHlwZSA8PCBSRElfQ0ZHMF9EVDsKPiArCXdyaXRlbCh2YWwsIGNzaWQtPmJhc2UgKyBDU0lEX1JE SV9DRkcwKHBvcnQpKTsKPiArCj4gKwl2YWwgPSBSRElfQ0ZHMV9QQUNLSU5HX0ZPUk1BVF9NSVBJ Owo+ICsJd3JpdGVsKHZhbCwgY3NpZC0+YmFzZSArIENTSURfUkRJX0NGRzEocG9ydCkpOwo+ICsK PiArCS8qIENvbmZpZ3VyZSBwaXhlbCBzdG9yZSB1c2luZyBkZWRpY2F0ZWQgcmVnaXN0ZXIgaW4g MTA4MCAqLwo+ICsJaWYgKCFjc2lkX2lzX2xpdGUoY3NpZCkpCj4gKwkJX19jc2lkX2NvbmZpZ3Vy ZV9yZGlfcGl4X3N0b3JlKGNzaWQsIHBvcnQpOwo+ICsKPiArCXZhbCA9IDA7Cj4gKwl3cml0ZWwo dmFsLCBjc2lkLT5iYXNlICsgQ1NJRF9SRElfQ1RSTChwb3J0KSk7Cj4gKwo+ICsJdmFsID0gcmVh ZGwoY3NpZC0+YmFzZSArIENTSURfUkRJX0NGRzAocG9ydCkpOwo+ICsKPiArCWlmIChlbmFibGUp Cj4gKwkJdmFsIHw9IFJESV9DRkcwX0VOOwo+ICsKPiArCXdyaXRlbCh2YWwsIGNzaWQtPmJhc2Ug KyBDU0lEX1JESV9DRkcwKHBvcnQpKTsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgY3NpZF9jb25m aWd1cmVfc3RyZWFtKHN0cnVjdCBjc2lkX2RldmljZSAqY3NpZCwgdTggZW5hYmxlKQo+ICt7Cj4g Kwl1OCBpLCBrOwo+ICsKPiArCV9fY3NpZF9jb25maWd1cmVfcngoY3NpZCwgJmNzaWQtPnBoeSk7 Cj4gKwo+ICsJZm9yIChpID0gMDsgaSA8IE1TTV9DU0lEX01BWF9TUkNfU1RSRUFNU18xMDgwOyBp KyspIHsKPiArCQlpZiAoY3NpZC0+cGh5LmVuX3ZjICYgQklUKGkpKSB7Cj4gKwkJCV9fY3NpZF9j b25maWd1cmVfcmRpX3N0cmVhbShjc2lkLCBlbmFibGUsIGksIDApOwoKW1NldmVyaXR5OiBIaWdo XQpDYW4gdGhpcyByZWFkIHBhc3QgdGhlIGVuZCBvZiBjc2lkLT5mbXRbXSBvbiBub24tbGl0ZSBD U0lEIDEwODAgaW5zdGFuY2VzPwoKRm9yIG5vbi1saXRlIGluc3RhbmNlcyAoQ1NJRDAsIENTSUQx LCBDU0lEMiBpbiBjc2lkX3Jlc19rYWFuYXBhbGkpLApNU01fQ1NJRF9NQVhfU1JDX1NUUkVBTVNf MTA4MCBldmFsdWF0ZXMgdG8gNSwgc28gY3NpZF9jb25maWd1cmVfc3RyZWFtKCkKaXRlcmF0ZXMg aSBmcm9tIDAgdG8gNCBhbmQgcGFzc2VzIHBvcnQgPSA0IGludG8KX19jc2lkX2NvbmZpZ3VyZV9y ZGlfc3RyZWFtKCkuCgpJbnNpZGUgX19jc2lkX2NvbmZpZ3VyZV9yZGlfc3RyZWFtKCksIGlucHV0 X2Zvcm1hdCBpcyBjb21wdXRlZCBhczoKCglzdHJ1Y3QgdjRsMl9tYnVzX2ZyYW1lZm10ICppbnB1 dF9mb3JtYXQgPSAmY3NpZC0+Zm10W01TTV9DU0lEX1BBRF9GSVJTVF9TUkMgKyBwb3J0XTsKCkhv d2V2ZXIsIGluIGRyaXZlcnMvbWVkaWEvcGxhdGZvcm0vcWNvbS9jYW1zcy9jYW1zcy1jc2lkLmgs Ck1TTV9DU0lEX1BBRF9GSVJTVF9TUkMgaXMgMSBhbmQgTVNNX0NTSURfUEFEU19OVU0gaXMgc3Rp bGwgNToKCgkjZGVmaW5lIE1TTV9DU0lEX1BBRF9TSU5LIDAKCSNkZWZpbmUgTVNNX0NTSURfUEFE X0ZJUlNUX1NSQyAxCgkjZGVmaW5lIE1TTV9DU0lEX1BBRFNfTlVNIDUKCS4uLgoJc3RydWN0IGNz aWRfZGV2aWNlIHsKCQkuLi4KCQlzdHJ1Y3QgbWVkaWFfcGFkIHBhZHNbTVNNX0NTSURfUEFEU19O VU1dOwoJCS4uLgoJCXN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQgZm10W01TTV9DU0lEX1BBRFNf TlVNXTsKCldoZW4gcG9ydCBpcyA0LCBNU01fQ1NJRF9QQURfRklSU1RfU1JDICsgcG9ydCBpcyA1 LCB3aGljaCBpbmRleGVzIG9uZQplbGVtZW50IHBhc3QgdGhlIGVuZCBvZiBjc2lkLT5mbXRbNV0g d2hlbiByZWFkaW5nIGlucHV0X2Zvcm1hdC0+Y29kZSAoYW5kCm1zbV9jc2lkX3JlZ2lzdGVyX2Vu dGl0eSgpIG9ubHkgcmVnaXN0ZXJzIDQgc291cmNlIHBhZHMpLiBTaG91bGQKTVNNX0NTSURfUEFE U19OVU0gYW5kIE1TTV9DU0lEX01BWF9TUkNfU1RSRUFNUyBiZSB1cGRhdGVkIHRvIGFjY29tbW9k YXRlCnRoZSA1dGggUkRJIHN0cmVhbSwgb3Igc2hvdWxkIE1TTV9DU0lEX01BWF9TUkNfU1RSRUFN U18xMDgwIGJlIGNhcHBlZCB0bwp0aGUgbnVtYmVyIG9mIHNvdXJjZSBwYWRzPwoKPiArCQkJX19j c2lkX2NvbmZpZ3VyZV9yeF92Yyhjc2lkLCAwKTsKPiArCj4gKwkJCWZvciAoayA9IDA7IGsgPCBD QU1TU19JTklUX0JVRl9DT1VOVDsgaysrKQo+ICsJCQkJX19jc2lkX2FkZHJfdXBkYXRlKGNzaWQs IGkpOwo+ICsKPiArCQkJX19jc2lkX3JlZ191cGRhdGUoY3NpZCwgaSk7Cj4gKwo+ICsJCQlfX2Nz aWRfY3RybF9yZGkoY3NpZCwgZW5hYmxlLCBpKTsKPiArCQl9Cj4gKwl9Cj4gK30KClsgLi4uIF0K Cj4gK3N0YXRpYyBpcnFyZXR1cm5fdCBjc2lkX2lzcihpbnQgaXJxLCB2b2lkICpkZXYpCj4gK3sK PiArCXN0cnVjdCBjc2lkX2RldmljZSAqY3NpZCA9IGRldjsKPiArCXUzMiB2YWwsIGJ1Zl9kb25l X3ZhbDsKPiArCXU4IHJlc2V0X2RvbmU7Cj4gKwlpbnQgaTsKPiArCj4gKwl2YWwgPSByZWFkbChj c2lkLT5iYXNlICsgQ1NJRF9UT1BfSVJRX1NUQVRVUyk7Cj4gKwl3cml0ZWwodmFsLCBjc2lkLT5i YXNlICsgQ1NJRF9UT1BfSVJRX0NMRUFSKTsKPiArCj4gKwlyZXNldF9kb25lID0gdmFsICYgSU5G T19SU1RfRE9ORTsKPiArCj4gKwlidWZfZG9uZV92YWwgPSByZWFkbChjc2lkLT5iYXNlICsgQ1NJ RF9CVUZfRE9ORV9JUlFfU1RBVFVTKTsKPiArCXdyaXRlbChidWZfZG9uZV92YWwsIGNzaWQtPmJh c2UgKyBDU0lEX0JVRl9ET05FX0lSUV9DTEVBUik7Cj4gKwo+ICsJZm9yIChpID0gMDsgaSA8IE1T TV9DU0lEX01BWF9TUkNfU1RSRUFNU18xMDgwOyBpKyspIHsKPiArCQlpZiAoY3NpZC0+cGh5LmVu X3ZjICYgQklUKGkpKSB7Cj4gKwkJCXZhbCA9IHJlYWRsKGNzaWQtPmJhc2UgKyBDU0lEX0NTSTJf UkRJTl9JUlFfU1RBVFVTKGkpKTsKPiArCQkJd3JpdGVsKHZhbCwgY3NpZC0+YmFzZSArIENTSURf Q1NJMl9SRElOX0lSUV9DTEVBUihpKSk7Cj4gKwo+ICsJCQlpZiAodmFsICYgSU5GT19SVVBfRE9O RSkgewo+ICsJCQkJX19jc2lkX2FkZHJfdXBkYXRlX2NsZWFyKGNzaWQsIGkpOwo+ICsJCQkJX19j c2lkX3JlZ191cGRhdGVfY2xlYXIoY3NpZCwgaSk7Cj4gKwkJCX0KPiArCj4gKwkJCWlmIChidWZf ZG9uZV92YWwgJiBCSVQoQlVGX0RPTkVfSVJRX1NUQVRVU19SRElfT0ZGU0VUICsgaSkpCj4gKwkJ CQljYW1zc19idWZfZG9uZShjc2lkLT5jYW1zcywgY3NpZC0+aWQsIGkpOwoKW1NldmVyaXR5OiBN ZWRpdW1dCkNvdWxkIHRoZSB1bmxvY2tlZCB1cGRhdGVzIHRvIGNzaWQtPmFkZHJfdXBkYXRlIGFu ZCBjc2lkLT5yZWdfdXBkYXRlIGhlcmUKcmFjZSB3aXRoIHZmZV9xdWV1ZV9idWZmZXJfdjIoKSBh bmQgdmZlX2VuYWJsZV9vdXRwdXRfdjIoKSwgb3IgcmUtdHJpZ2dlcgp1cGRhdGVzIGZvciBvdGhl ciBSREkgcG9ydHM/CgpJbiBkcml2ZXJzL21lZGlhL3BsYXRmb3JtL3Fjb20vY2Ftc3MvY2Ftc3Mt dmZlLmMsIHZmZV9xdWV1ZV9idWZmZXJfdjIoKSBhbmQKdmZlX2VuYWJsZV9vdXRwdXRfdjIoKSBj YWxsIG9wcy0+YWRkcl91cGRhdGUoKSBhbmQgb3BzLT5yZWdfdXBkYXRlKCkgd2hpbGUKaG9sZGlu ZyB2ZmUtPm91dHB1dF9sb2NrOgoKCXZmZV9xdWV1ZV9idWZmZXJfdjIoKQoJICBzcGluX2xvY2tf aXJxc2F2ZSgmdmZlLT5vdXRwdXRfbG9jaywgZmxhZ3MpOwoJICBvcHMtPmFkZHJfdXBkYXRlKHZm ZSwgbGluZS0+aWQpCgkgICAgLT4gY3NpZF9zdWJkZXZfYWRkcl91cGRhdGUoKQoJICAgICAgLT4g X19jc2lkX2FkZHJfdXBkYXRlKCkKCSAgb3BzLT5yZWdfdXBkYXRlKHZmZSwgbGluZS0+aWQpCgkg ICAgLT4gY3NpZF9zdWJkZXZfcmVnX3VwZGF0ZSgpCgkgICAgICAtPiBfX2NzaWRfcmVnX3VwZGF0 ZSgpCgpJbiBjc2lkX2lzcigpLCBfX2NzaWRfYWRkcl91cGRhdGVfY2xlYXIoKSBhbmQgX19jc2lk X3JlZ191cGRhdGVfY2xlYXIoKQptb2RpZnkgY3NpZC0+YWRkcl91cGRhdGUgYW5kIGNzaWQtPnJl Z191cGRhdGUgd2l0aG91dCBob2xkaW5nCnZmZS0+b3V0cHV0X2xvY2sgb3IgYSBDU0lEIHNwaW5s b2NrLiBJZiBjc2lkX2lzcigpIHJ1bnMgb24gb25lIENQVSB3aGlsZQp2ZmVfcXVldWVfYnVmZmVy X3YyKCkgb3IgdmZlX2VuYWJsZV9vdXRwdXRfdjIoKSBydW5zIG9uIGFub3RoZXIgQ1BVLCB0aGUK cmVhZC1tb2RpZnktd3JpdGUgb24gY3NpZC0+YWRkcl91cGRhdGUgYW5kIGNzaWQtPnJlZ191cGRh dGUgY2FuIGxvc2UgYQpuZXdseSBzZXQgUkRJIGJpdCBvciB3cml0ZSBhIHN0YWxlIGNsZWFyZWQg Yml0IGJhY2sgaW50byBDU0lEX0FVUF9DTUQgYW5kCkNTSURfUlVQX0NNRC4KCkFsc28sIHdpdGhp biB0aGlzIGxvb3AgaW4gY3NpZF9pc3IoKSwgY2Ftc3NfYnVmX2RvbmUoKSAtPiB2ZmVfYnVmX2Rv bmUoKSBpcwpjYWxsZWQgZm9yIHBvcnQgaSBiZWZvcmUgSU5GT19SVVBfRE9ORSBpcyBjaGVja2Vk IGFuZCBjbGVhcmVkIGZvciBwb3J0cwpqID4gaS4gV2hlbiB2ZmVfYnVmX2RvbmUoKSBjYWxscyBf X2NzaWRfYWRkcl91cGRhdGUoY3NpZCwgaSksIGl0IHdyaXRlcyB0aGUKZW50aXJlIGNzaWQtPmFk ZHJfdXBkYXRlIGJpdG1hc2sgdG8gQ1NJRF9BVVBfQ01EIHdoaWxlIGNvbXBsZXRlZCBwb3J0cwpq ID4gaSBzdGlsbCBoYXZlIHRoZWlyIENTSURfUlVQX0FVUF9SREkoaikgYml0cyBzZXQuIFNob3Vs ZCBJTkZPX1JVUF9ET05FCmJlIHByb2Nlc3NlZCBmb3IgYWxsIHBvcnRzIGJlZm9yZSBpbnZva2lu ZyBjYW1zc19idWZfZG9uZSgpLCBvciBkb2VzCkNTSURfQVVQX0NNRCAvIENTSURfUlVQX0NNRCBv bmx5IG5lZWQgQ1NJRF9SVVBfQVVQX1JESShwb3J0X2lkKSB3cml0dGVuCmRpcmVjdGx5PwoKLS0g ClNhc2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2FzaGlrby5kZXYvIy9wYXRjaHNldC8yMDI2 MTAyOC1rYWFuYXBhbGktY2Ftc3MtdjIzLTAtOTVmMjUwYjE4NjEyQG9zcy5xdWFsY29tbS5jb20/ cGFydD05CgotLSAKbGludXgtcGh5IG1haWxpbmcgbGlzdApsaW51eC1waHlAbGlzdHMuaW5mcmFk ZWFkLm9yZwpodHRwczovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51 eC1waHkK