From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793202361; b=HtjueurNsd3x/g9RDzyzkjKc+2T1NTCIAhpqhTXvJeFTS5GOWNgH+YAdBuue5pRtFy63 KoGUcESNFFWrhd24he/pOBqvUvkye0VSMhRSAn2M1/zRx2qxG+ON0YKxE/yS8dEsv1LFs G9pHGv2idUe8kqOAk7zfpX3C1MmsmKW0VLrrajUaYejJlAXhMYM/bJncUJ+UXDuYOI2F6 sJ9z48w0cEkJ7K1tnl5GoVNzKDzaDWBk8mKUzBJbk/j7Hfns7rH7BUs3FM21KJ8UcB3cd pzn4spMjnhfR8bGNi0vYs6OcXM8Q3p5h+eySB+XiKSwYOhodXwqnktZc2KuMdJLNdRA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793202361; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=HvHC2Ot2Ch3mXIf1DlX2QOM69UyxffuDNqpJNIhZ6TY=; b=Nu2UDW6sSENua6POy4skcDQJ9dSyUCb7cTg+sthxoY+9wVHRT5Bw0eadQwYYq76A593b 4hGbwOPXm3Sj+TdtQPy++2HBXXydDh8zRKyytO0xBmVprZEzgm+Rtniyoxh/drSy6WLn8 Rdo7PSyXd+Fo+/H8CcYcmx269moF5umjJGJ2x1uPdplRWn6hea1ta9/QHo9QJIVWq1O91 cnHfgGnBEYeKk6trvmxzTxDqWVZ2PWajOYPBqIoPG/Ko2v6jpz8oOqnfNfycnakzU4wIb bUAaGd7Ga1BJkZUEIHMNTwZLYmECxWDH4g1i9dUOcbYDe9+EcTUWYrV5fnAVMjmoIhQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b="B1C/xRZl"; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CD07606A32C for ; Wed, 28 Oct 2026 15:46:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=B1C/xRZl Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6E7D31F01828; Wed, 28 Oct 2026 15:46:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793202360; bh=HvHC2Ot2Ch3mXIf1DlX2QOM69UyxffuDNqpJNIhZ6TY=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=B1C/xRZljz/YnBrL3OzjwDSAWCJYD/pFXdS4MlTuqRmfLA+GfNZXkUBWE/EqKC14g t/XxH+9E3wPy1OXiYkjuHYXqbhY16MYE4GaI5nIEnDFiYSD3OK0oGxQK6q2goyGY0k WR5icFvWOF+TsgRKyqalVXKKolsnoZOxNG3JGd1FFbRaNu4Ihllko35iBdyg6FK+2h G13tZ7+fLwVh8Xa/mOZj5UZNKWOpMz+vSDwVtlf/qQJlUCJcWR9f6GKzmGaGKeuifv DeAq+i21Aakf1h5b12bKDEaohg2Bbjte/jGdw+FMTd8DtrGJNVsLUQuTtstXxIAi0E cC74vdi/0/I1w== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v6 4/5] phy: starfive: Add jh7110-inno-hdmi-phy driver Reply-To: sashiko-reviews@lists.linux.dev To: "Michal Wilczynski" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261028-jh7110-inno-hdmi-phy-v6-4-f3379684d97e@samsung.com> References: <20261028-jh7110-inno-hdmi-phy-v6-0-f3379684d97e@samsung.com> <20261028-jh7110-inno-hdmi-phy-v6-4-f3379684d97e@samsung.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Wed, 28 Oct 2026 15:46:00 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 4 potential issue(= s) to consider: - [High] phy: starfive: hdmi: fix rate cache and BIAS/RX state across disab= le/enable - [High] phy: starfive: jh7110-inno-hdmi: invalid pre_pll_cfg_table divider= values - [Medium] phy: starfive: jh7110-inno-hdmi: broken Pre-PLL power and lock s= equencing in clk_ops - [Low] phy: starfive: unused inno_read() helper and register macros in hdm= i phy -- commit de90e248a2b1a2d110bed58fd3d5de2e75a01d3d Author: Michal Wilczynski phy: starfive: Add jh7110-inno-hdmi-phy driver This commit adds the Innosilicon HDMI PHY driver for the StarFive JH7110 So= C. The driver acts as both a clock provider for the variable pixel clock via t= he Pre-PLL and a PHY provider configuring the Post-PLL and analog blocks. > diff --git a/drivers/phy/starfive/phy-jh7110-inno-hdmi.c b/drivers/phy/st= arfive/phy-jh7110-inno-hdmi.c > new file mode 100644 > index 0000000000000..ebda363e50a3e > --- /dev/null > +++ b/drivers/phy/starfive/phy-jh7110-inno-hdmi.c [ ... ] > +/* REG: 0x1aa */ > +#define STF_INNO_POST_PLL_DIV_1 0x1aa > +#define STF_INNO_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2) > +#define STF_INNO_POST_PLL_REFCLK_SEL_TMDS BIT(1) > +#define STF_INNO_POST_PLL_POWER_DOWN BIT(0) > + > +/* REG: 0x1ab */ > +#define STF_INNO_POST_PLL_DIV_2 0x1ab > +#define STF_INNO_POST_PLL_PRE_DIV(x) FIELD_PREP(GENMASK(5, 0), x) > +#define STF_INNO_POST_PLL_FB_DIV_8(x) FIELD_PREP(BIT(7), (x) >> 8) > + > +/* REG: 0x1ac */ > +#define STF_INNO_POST_PLL_DIV_3 0x1ac > +#define STF_INNO_POST_PLL_FB_DIV_7_0(x) FIELD_PREP(GENMASK(7, 0), x) > + > +/* REG: 0x1ad */ > +#define STF_INNO_POST_PLL_DIV_4 0x1ad > +#define STF_INNO_POST_PLL_POST_DIV_MASK GENMASK(1, 0) > + > +/* REG: 0x1af */ > +#define STF_INNO_POST_PLL_LOCK_STATUS 0x1af > +#define STF_INNO_POST_PLL_LOCK BIT(0) > + > +/* REG: 0x1b0 */ > +#define STF_INNO_BIAS_CONTROL 0x1b0 > +#define STF_INNO_BIAS_ENABLE BIT(2) > + > +/* REG: 0x1b2 */ > +#define STF_INNO_TMDS_CONTROL 0x1b2 > +#define STF_INNO_TMDS_CLK_DRIVER_EN BIT(3) > +#define STF_INNO_TMDS_D2_DRIVER_EN BIT(2) > +#define STF_INNO_TMDS_D1_DRIVER_EN BIT(1) > +#define STF_INNO_TMDS_D0_DRIVER_EN BIT(0) > +#define STF_INNO_TMDS_DRIVER_ENABLE (STF_INNO_TMDS_CLK_DRIVER_EN | \ > + STF_INNO_TMDS_D2_DRIVER_EN | \ > + STF_INNO_TMDS_D1_DRIVER_EN | \ > + STF_INNO_TMDS_D0_DRIVER_EN) [ ... ] > +static const struct inno_hdmi_phy_pre_pll_config pre_pll_cfg_table[] =3D= { > + { 25175000, 25175000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0xf55555 }, > + { 25200000, 25200000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0 }, > + { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0 }, > + { 27027000, 27027000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0x170a3d }, > + { 28320000, 28320000, 1, 28, 2, 1, 1, 3, 0, 3, 4, 0, 0x51eb85 }, > + { 30240000, 30240000, 1, 30, 2, 1, 1, 3, 0, 3, 4, 0, 0x3d70a3 }, > + { 31500000, 31500000, 1, 31, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff }, > + { 33750000, 33750000, 1, 33, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff }, [ ... ] > + { 78750000, 78750000, 1, 78, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff }, [ ... ] > + { 85750000, 85750000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff }, > + { 85800000, 85800000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xcccccc }, > + { 88750000, 88750000, 1, 88, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff }, [ ... ] > + { 136750000, 136750000, 1, 136, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff }, [ ... ] > + { 262750000, 262750000, 1, 262, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff }, [Severity: High] Do these eight entries in pre_pll_cfg_table generate the wrong pixel clock and cause starfive_hdmi_phy_power_on() to fail with -EINVAL? With the 24 MHz reference clock: - 25175000 has div =3D 1 * 12 * 4 * 2 =3D 96, so 24 MHz * (100 + 0xf55555 /= 2^24) / 96 yields 25,239,583 Hz, which inno_hdmi_phy_pre_pll_recalc_rate() recalculates as 25240000 Hz. - 25200000 has div =3D 96 and fracdiv =3D 0, so 24 MHz * 100 / 96 yields 25000000 Hz. - 33750000, 78750000, 85750000, 88750000, 136750000, and 262750000 have div =3D 1 * 3 * 4 * 2 =3D 24 and fracdiv =3D 0xcfffff (~0.8125 instead of 0xc00000 =3D 0.75), which adds 812.5 kHz instead of 750 kHz and recalcula= tes to 33812000, 78812000, 85812000, 88812000, 136812000, and 262812000 Hz. When hdmi_pclk is prepared and starfive_hdmi_phy_clk_recalc_rate() runs: clk_change_rate() clk_recalc() starfive_hdmi_phy_clk_recalc_rate() inno_hdmi_phy_pre_pll_recalc_rate() the clock framework caches the recalculated rate in core->rate. When starfive_hdmi_phy_power_on() then calls: tmdsclock =3D clk_get_rate(inno->phyclk); pre_cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, tmdsclock, tmdsclock); inno_hdmi_phy_pre_pll_lookup() requires an exact match against cfg->pixclock in pre_pll_cfg_table, which fails with -EINVAL for all eight modes. [ ... ] > +static inline void inno_write(struct starfive_hdmi_phy *inno, u32 reg, u= 8 val) > +{ > + regmap_write(inno->regmap, reg * 4, val); > +} > + > +static inline u8 inno_read(struct starfive_hdmi_phy *inno, u32 reg) > +{ > + u32 val; > + > + regmap_read(inno->regmap, reg * 4, &val); > + return val; > +} [Severity: Low] Is inno_read() needed here? It is never called in this file, and the register bit macros STF_INNO_POST_PLL_POST_DIV_ENABLE, STF_INNO_POST_PLL_REFCLK_SEL_TMDS, STF_INNO_POST_PLL_FB_DIV_8, STF_INNO_POST_PLL_FB_DIV_7_0, STF_INNO_POST_PLL_POST_DIV_MASK, and STF_INNO_TMDS_DRIVER_ENABLE defined at the top of the file are also unused (while starfive_hdmi_phy_power_on() open-codes 0x0e, 0x02, cfg->fbdiv & 0xf= f, and 0x8f), which triggers compiler warnings under W=3D2 builds. [ ... ] > +static int starfive_hdmi_phy_clk_prepare(struct clk_hw *hw) > +{ > + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); > + int ret; > + > + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); > + > + if (inno_hdmi_phy_pre_pll_is_locked(&inno->pre_pll)) > + return 0; > + > + ret =3D inno_hdmi_phy_pre_pll_wait_locked(&inno->pre_pll, 100000); > + if (ret) { > + dev_err(inno->dev, "Timeout waiting for pre-PLL lock\n"); > + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); > + return ret; > + } > + > + return 0; > +} > + > +static void starfive_hdmi_phy_clk_unprepare(struct clk_hw *hw) > +{ > + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); > + > + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); > + inno->pixclock =3D 0; /* Invalidate cached rate */ > +} > + > +static unsigned long starfive_hdmi_phy_clk_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); > + > + /* > + * Reading the PLL back requires the HDMI controller's system clock, > + * which the sibling controller driver holds and this driver cannot > + * request without creating a probe cycle with voutcrg. The clock > + * framework walks every registered clock regardless of which drivers > + * have bound, so fall back to the cached rate whenever this clock is > + * not prepared; an unclocked access to the shared register window > + * wedges the bus hard enough that the CPU stops taking NMIs. > + */ > + if (!clk_hw_is_prepared(hw)) > + return inno->pixclock; > + > + inno->pixclock =3D inno_hdmi_phy_pre_pll_recalc_rate(&inno->pre_pll, > + parent_rate); > + > + return inno->pixclock; > +} [ ... ] > +static int starfive_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned lo= ng rate, > + unsigned long parent_rate) > +{ > + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); > + const struct inno_hdmi_phy_pre_pll_config *cfg; > + > + /* > + * The JH7110 only drives 8bpc, so the TMDS clock always matches the > + * pixel clock. > + */ > + cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, rate, rate); > + if (IS_ERR(cfg)) > + return PTR_ERR(cfg); > + > + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", > + __func__, rate, cfg->tmdsclock); > + > + if (inno->pixclock =3D=3D rate && inno->tmdsclock =3D=3D cfg->tmdsclock) > + return 0; > + > + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, > + STF_INNO_BIAS_ENABLE, STF_INNO_BIAS_ENABLE); > + inno_write(inno, STF_INNO_RX_CONTROL, STF_INNO_RX_ENABLE); > + > + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); > + inno_hdmi_phy_pre_pll_configure(&inno->pre_pll, cfg); > + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); > + > + inno->pixclock =3D rate; > + inno->tmdsclock =3D cfg->tmdsclock; > + > + return 0; > +} [Severity: Medium] Should starfive_hdmi_phy_clk_set_rate() wait for the Pre-PLL to lock or keep it powered down when the clock is unprepared? In starfive_hdmi_phy_clk_set_rate(), the driver powers down the Pre-PLL, configures it, and powers it back up via inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false), returning 0 without calling inno_hdmi_phy_pre_pll_wait_locked(). If clk_set_rate() is called while hdmi_pclk is already prepared, starfive_hdmi_phy_clk_prepare() is not called again because prepare_count is already non-zero, so nothing waits for the Pre-PLL to lock before starfive_hdmi_phy_power_on() configures and enables the Post-PLL (which uses the Pre-PLL TMDS clock as its reference). Conversely, if clk_set_rate() is called while hdmi_pclk is unprepared, starfive_hdmi_phy_clk_set_rate() leaves the Pre-PLL, STF_INNO_BIAS_ENABLE, and STF_INNO_RX_ENABLE powered on in hardware while prepare_count is 0. > + > +static const struct clk_ops starfive_hdmi_phy_clk_ops =3D { > + .prepare =3D starfive_hdmi_phy_clk_prepare, > + .unprepare =3D starfive_hdmi_phy_clk_unprepare, > + .recalc_rate =3D starfive_hdmi_phy_clk_recalc_rate, > + .determine_rate =3D starfive_hdmi_phy_clk_determine_rate, > + .set_rate =3D starfive_hdmi_phy_clk_set_rate, > +}; > + > +static void starfive_hdmi_phy_power_down(struct starfive_hdmi_phy *inno) > +{ > + inno_write(inno, STF_INNO_TMDS_CONTROL, 0x00); > + inno_write(inno, STF_INNO_SERIALIER_CONTROL, 0x00); > + inno_write(inno, STF_INNO_LDO_CONTROL, 0x00); > + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, > + STF_INNO_BIAS_ENABLE, 0x00); > + inno_write(inno, STF_INNO_RX_CONTROL, 0x00); > + > + /* Power down Post-PLL */ > + inno_update_bits(inno, STF_INNO_POST_PLL_DIV_1, > + STF_INNO_POST_PLL_POWER_DOWN, > + STF_INNO_POST_PLL_POWER_DOWN); > + > + inno->tmdsclock =3D 0; > + inno->pixclock =3D 0; > +} [Severity: High] What happens when HDMI output is disabled and then re-enabled at the same pixel clock rate? When the display is disabled: 1. starfive_hdmi_phy_power_off() -> starfive_hdmi_phy_power_down() clears STF_INNO_BIAS_ENABLE and STF_INNO_RX_CONTROL to 0, and sets inno->tmdsclock =3D 0 and inno->pixclock =3D 0. 2. clk_disable_unprepare() -> starfive_hdmi_phy_clk_unprepare() powers down the Pre-PLL and sets inno->pixclock =3D 0. However, clk_core_unprepare() in the clock framework does not clear core->rate, so the clock framework still caches the previous rate R. When the display is re-enabled at the same rate R: 1. clk_set_rate(phyclk, R) sees rate =3D=3D clk_core_get_rate_nolock(core) = in clk_core_set_rate_nolock() and returns 0 early without calling starfive_hdmi_phy_clk_set_rate(). 2. clk_prepare_enable(phyclk) calls starfive_hdmi_phy_clk_prepare() before phy_power_on(), powering up the Pre-PLL and polling inno_hdmi_phy_pre_pll_wait_locked() while STF_INNO_BIAS_ENABLE and STF_INNO_RX_ENABLE are still disabled at 0 (and without reprogramming the Pre-PLL if the shared register block was reset). Additionally, if a clock tree walk invokes starfive_hdmi_phy_clk_recalc_rat= e() while phyclk is unprepared after inno->pixclock was zeroed, it returns 0 and overwrites core->rate with 0. If the display is then re-enabled without a n= ew clk_set_rate() call, clk_get_rate(inno->phyclk) in starfive_hdmi_phy_power_on() returns 0 and fails inno_hdmi_phy_pre_pll_lookup() with -EINVAL. --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261028-jh7110-inn= o-hdmi-phy-v6-0-f3379684d97e@samsung.com?part=3D4 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3371F606A32C for ; Wed, 28 Oct 2026 15:46:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=C9eGeiVY; dkim=fail reason="signature verification failed" (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=B1C/xRZl DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Date:References: In-Reply-To:Cc:To:Subject:From:Message-ID:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Unsubscribe-Post:List-Owner; bh=lovPEeQsKDqqroyGhkPkEnpwcPjI8aG7y2Cah5IA9j0=; b=C9eGeiVYu8ZTt3a2tM3nk0yafT ck3cq5Wdi2g2iKLAig2yp3hT3+lbqzyyffQ7MgryA1xiRYGyBlUjp1fppKDRgqfnBBxN0V2ZVCDoq qGTAfg+6BzAJ86jQNw9TEJf6zLRyzyXsYBlClzvTd5KZXxASkI8LjC+mMFPIor4G9iyv0om/CmP/A 4OK9bpl7oEucKt+h1PvI9OtZiPogFS+s7faLlIm5M6bT6j6mdI4ClhycfGzKY/OVLkxV6CLSpcxx5 tbeP4Be3C/bJQc3gUCk1A0KRSRk4l3RpFRAvQj7mmsKlgGgYRk2X0GztcMrSftvxrxra4wJIvQPmB S2vl3RTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xM5qk-00000007SKM-3pI1; Wed, 28 Oct 2026 15:46:02 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xM5qk-00000007SK0-0eYg for linux-phy@lists.infradead.org; Wed, 28 Oct 2026 15:46:02 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 1CF27600DA; Wed, 28 Oct 2026 15:46:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6E7D31F01828; Wed, 28 Oct 2026 15:46:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793202360; bh=HvHC2Ot2Ch3mXIf1DlX2QOM69UyxffuDNqpJNIhZ6TY=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=B1C/xRZljz/YnBrL3OzjwDSAWCJYD/pFXdS4MlTuqRmfLA+GfNZXkUBWE/EqKC14g t/XxH+9E3wPy1OXiYkjuHYXqbhY16MYE4GaI5nIEnDFiYSD3OK0oGxQK6q2goyGY0k WR5icFvWOF+TsgRKyqalVXKKolsnoZOxNG3JGd1FFbRaNu4Ihllko35iBdyg6FK+2h G13tZ7+fLwVh8Xa/mOZj5UZNKWOpMz+vSDwVtlf/qQJlUCJcWR9f6GKzmGaGKeuifv DeAq+i21Aakf1h5b12bKDEaohg2Bbjte/jGdw+FMTd8DtrGJNVsLUQuTtstXxIAi0E cC74vdi/0/I1w== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v6 4/5] phy: starfive: Add jh7110-inno-hdmi-phy driver To: "Michal Wilczynski" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261028-jh7110-inno-hdmi-phy-v6-4-f3379684d97e@samsung.com> References: <20261028-jh7110-inno-hdmi-phy-v6-0-f3379684d97e@samsung.com> <20261028-jh7110-inno-hdmi-phy-v6-4-f3379684d97e@samsung.com> Date: Wed, 28 Oct 2026 15:46:00 +0000 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg NCBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIHBoeTogc3RhcmZpdmU6 IGhkbWk6IGZpeCByYXRlIGNhY2hlIGFuZCBCSUFTL1JYIHN0YXRlIGFjcm9zcyBkaXNhYmxlL2Vu YWJsZQotIFtIaWdoXSBwaHk6IHN0YXJmaXZlOiBqaDcxMTAtaW5uby1oZG1pOiBpbnZhbGlkIHBy ZV9wbGxfY2ZnX3RhYmxlIGRpdmlkZXIgdmFsdWVzCi0gW01lZGl1bV0gcGh5OiBzdGFyZml2ZTog amg3MTEwLWlubm8taGRtaTogYnJva2VuIFByZS1QTEwgcG93ZXIgYW5kIGxvY2sgc2VxdWVuY2lu ZyBpbiBjbGtfb3BzCi0gW0xvd10gcGh5OiBzdGFyZml2ZTogdW51c2VkIGlubm9fcmVhZCgpIGhl bHBlciBhbmQgcmVnaXN0ZXIgbWFjcm9zIGluIGhkbWkgcGh5Ci0tCgpjb21taXQgZGU5MGUyNDhh MmIxYTJkMTEwYmVkNThmZDNkNWRlMmU3NWEwMWQzZApBdXRob3I6IE1pY2hhbCBXaWxjenluc2tp IDxtLndpbGN6eW5za2lAc2Ftc3VuZy5jb20+CgpwaHk6IHN0YXJmaXZlOiBBZGQgamg3MTEwLWlu bm8taGRtaS1waHkgZHJpdmVyCgpUaGlzIGNvbW1pdCBhZGRzIHRoZSBJbm5vc2lsaWNvbiBIRE1J IFBIWSBkcml2ZXIgZm9yIHRoZSBTdGFyRml2ZSBKSDcxMTAgU29DLgpUaGUgZHJpdmVyIGFjdHMg YXMgYm90aCBhIGNsb2NrIHByb3ZpZGVyIGZvciB0aGUgdmFyaWFibGUgcGl4ZWwgY2xvY2sgdmlh IHRoZQpQcmUtUExMIGFuZCBhIFBIWSBwcm92aWRlciBjb25maWd1cmluZyB0aGUgUG9zdC1QTEwg YW5kIGFuYWxvZyBibG9ja3MuCgo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BoeS9zdGFyZml2ZS9w aHktamg3MTEwLWlubm8taGRtaS5jIGIvZHJpdmVycy9waHkvc3RhcmZpdmUvcGh5LWpoNzExMC1p bm5vLWhkbWkuYwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMDAwMDAwMC4u ZWJkYTM2M2U1MGEzZQo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2ZXJzL3BoeS9zdGFyZml2 ZS9waHktamg3MTEwLWlubm8taGRtaS5jClsgLi4uIF0KPiArLyogUkVHOiAweDFhYSAqLwo+ICsj ZGVmaW5lIFNURl9JTk5PX1BPU1RfUExMX0RJVl8xCQkweDFhYQo+ICsjZGVmaW5lIFNURl9JTk5P X1BPU1RfUExMX1BPU1RfRElWX0VOQUJMRQlHRU5NQVNLKDMsIDIpCj4gKyNkZWZpbmUgU1RGX0lO Tk9fUE9TVF9QTExfUkVGQ0xLX1NFTF9UTURTCUJJVCgxKQo+ICsjZGVmaW5lIFNURl9JTk5PX1BP U1RfUExMX1BPV0VSX0RPV04JCUJJVCgwKQo+ICsKPiArLyogUkVHOiAweDFhYiAqLwo+ICsjZGVm aW5lIFNURl9JTk5PX1BPU1RfUExMX0RJVl8yCQkweDFhYgo+ICsjZGVmaW5lIFNURl9JTk5PX1BP U1RfUExMX1BSRV9ESVYoeCkJCUZJRUxEX1BSRVAoR0VOTUFTSyg1LCAwKSwgeCkKPiArI2RlZmlu ZSBTVEZfSU5OT19QT1NUX1BMTF9GQl9ESVZfOCh4KQkJRklFTERfUFJFUChCSVQoNyksICh4KSA+ PiA4KQo+ICsKPiArLyogUkVHOiAweDFhYyAqLwo+ICsjZGVmaW5lIFNURl9JTk5PX1BPU1RfUExM X0RJVl8zCQkweDFhYwo+ICsjZGVmaW5lIFNURl9JTk5PX1BPU1RfUExMX0ZCX0RJVl83XzAoeCkJ RklFTERfUFJFUChHRU5NQVNLKDcsIDApLCB4KQo+ICsKPiArLyogUkVHOiAweDFhZCAqLwo+ICsj ZGVmaW5lIFNURl9JTk5PX1BPU1RfUExMX0RJVl80CQkweDFhZAo+ICsjZGVmaW5lIFNURl9JTk5P X1BPU1RfUExMX1BPU1RfRElWX01BU0sJR0VOTUFTSygxLCAwKQo+ICsKPiArLyogUkVHOiAweDFh ZiAqLwo+ICsjZGVmaW5lIFNURl9JTk5PX1BPU1RfUExMX0xPQ0tfU1RBVFVTCQkweDFhZgo+ICsj ZGVmaW5lIFNURl9JTk5PX1BPU1RfUExMX0xPQ0sJCUJJVCgwKQo+ICsKPiArLyogUkVHOiAweDFi MCAqLwo+ICsjZGVmaW5lIFNURl9JTk5PX0JJQVNfQ09OVFJPTAkJCTB4MWIwCj4gKyNkZWZpbmUg U1RGX0lOTk9fQklBU19FTkFCTEUJCQlCSVQoMikKPiArCj4gKy8qIFJFRzogMHgxYjIgKi8KPiAr I2RlZmluZSBTVEZfSU5OT19UTURTX0NPTlRST0wJCQkweDFiMgo+ICsjZGVmaW5lIFNURl9JTk5P X1RNRFNfQ0xLX0RSSVZFUl9FTgkJQklUKDMpCj4gKyNkZWZpbmUgU1RGX0lOTk9fVE1EU19EMl9E UklWRVJfRU4JCUJJVCgyKQo+ICsjZGVmaW5lIFNURl9JTk5PX1RNRFNfRDFfRFJJVkVSX0VOCQlC SVQoMSkKPiArI2RlZmluZSBTVEZfSU5OT19UTURTX0QwX0RSSVZFUl9FTgkJQklUKDApCj4gKyNk ZWZpbmUgU1RGX0lOTk9fVE1EU19EUklWRVJfRU5BQkxFCQkoU1RGX0lOTk9fVE1EU19DTEtfRFJJ VkVSX0VOIHwgXAo+ICsJCQkJCQkgU1RGX0lOTk9fVE1EU19EMl9EUklWRVJfRU4gfCBcCj4gKwkJ CQkJCSBTVEZfSU5OT19UTURTX0QxX0RSSVZFUl9FTiB8IFwKPiArCQkJCQkJIFNURl9JTk5PX1RN RFNfRDBfRFJJVkVSX0VOKQpbIC4uLiBdCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgaW5ub19oZG1p X3BoeV9wcmVfcGxsX2NvbmZpZyBwcmVfcGxsX2NmZ190YWJsZVtdID0gewo+ICsJeyAyNTE3NTAw MCwgMjUxNzUwMDAsIDEsIDEwMCwgMiwgMywgMywgMTIsIDMsIDMsIDQsIDAsIDB4ZjU1NTU1IH0s Cj4gKwl7IDI1MjAwMDAwLCAyNTIwMDAwMCwgMSwgMTAwLCAyLCAzLCAzLCAxMiwgMywgMywgNCwg MCwgMCB9LAo+ICsJeyAyNzAwMDAwMCwgMjcwMDAwMDAsIDEsIDkwLCAzLCAyLCAyLCAxMCwgMywg MywgNCwgMCwgMCB9LAo+ICsJeyAyNzAyNzAwMCwgMjcwMjcwMDAsIDEsIDkwLCAzLCAyLCAyLCAx MCwgMywgMywgNCwgMCwgMHgxNzBhM2QgfSwKPiArCXsgMjgzMjAwMDAsIDI4MzIwMDAwLCAxLCAy OCwgMiwgMSwgMSwgMywgMCwgMywgNCwgMCwgMHg1MWViODUgfSwKPiArCXsgMzAyNDAwMDAsIDMw MjQwMDAwLCAxLCAzMCwgMiwgMSwgMSwgMywgMCwgMywgNCwgMCwgMHgzZDcwYTMgfSwKPiArCXsg MzE1MDAwMDAsIDMxNTAwMDAwLCAxLCAzMSwgMiwgMSwgMSwgMywgMCwgMywgNCwgMCwgMHg3ZmZm ZmYgfSwKPiArCXsgMzM3NTAwMDAsIDMzNzUwMDAwLCAxLCAzMywgMiwgMSwgMSwgMywgMCwgMywg NCwgMCwgMHhjZmZmZmYgfSwKWyAuLi4gXQo+ICsJeyA3ODc1MDAwMCwgNzg3NTAwMDAsIDEsIDc4 LCAyLCAxLCAxLCAzLCAwLCAzLCA0LCAwLCAweGNmZmZmZiB9LApbIC4uLiBdCj4gKwl7IDg1NzUw MDAwLCA4NTc1MDAwMCwgMSwgODUsIDIsIDEsIDEsIDMsIDAsIDMsIDQsIDAsIDB4Y2ZmZmZmIH0s Cj4gKwl7IDg1ODAwMDAwLCA4NTgwMDAwMCwgMSwgODUsIDIsIDEsIDEsIDMsIDAsIDMsIDQsIDAs IDB4Y2NjY2NjIH0sCj4gKwl7IDg4NzUwMDAwLCA4ODc1MDAwMCwgMSwgODgsIDIsIDEsIDEsIDMs IDAsIDMsIDQsIDAsIDB4Y2ZmZmZmIH0sClsgLi4uIF0KPiArCXsgMTM2NzUwMDAwLCAxMzY3NTAw MDAsIDEsIDEzNiwgMiwgMSwgMSwgMywgMCwgMywgNCwgMCwgMHhjZmZmZmYgfSwKWyAuLi4gXQo+ ICsJeyAyNjI3NTAwMDAsIDI2Mjc1MDAwMCwgMSwgMjYyLCAyLCAxLCAxLCAzLCAwLCAzLCA0LCAw LCAweGNmZmZmZiB9LAoKW1NldmVyaXR5OiBIaWdoXQpEbyB0aGVzZSBlaWdodCBlbnRyaWVzIGlu IHByZV9wbGxfY2ZnX3RhYmxlIGdlbmVyYXRlIHRoZSB3cm9uZyBwaXhlbCBjbG9jawphbmQgY2F1 c2Ugc3RhcmZpdmVfaGRtaV9waHlfcG93ZXJfb24oKSB0byBmYWlsIHdpdGggLUVJTlZBTD8KCldp dGggdGhlIDI0IE1IeiByZWZlcmVuY2UgY2xvY2s6Ci0gMjUxNzUwMDAgaGFzIGRpdiA9IDEgKiAx MiAqIDQgKiAyID0gOTYsIHNvIDI0IE1IeiAqICgxMDAgKyAweGY1NTU1NSAvIDJeMjQpCiAgLyA5 NiB5aWVsZHMgMjUsMjM5LDU4MyBIeiwgd2hpY2ggaW5ub19oZG1pX3BoeV9wcmVfcGxsX3JlY2Fs Y19yYXRlKCkKICByZWNhbGN1bGF0ZXMgYXMgMjUyNDAwMDAgSHouCi0gMjUyMDAwMDAgaGFzIGRp diA9IDk2IGFuZCBmcmFjZGl2ID0gMCwgc28gMjQgTUh6ICogMTAwIC8gOTYgeWllbGRzCiAgMjUw MDAwMDAgSHouCi0gMzM3NTAwMDAsIDc4NzUwMDAwLCA4NTc1MDAwMCwgODg3NTAwMDAsIDEzNjc1 MDAwMCwgYW5kIDI2Mjc1MDAwMCBoYXZlCiAgZGl2ID0gMSAqIDMgKiA0ICogMiA9IDI0IGFuZCBm cmFjZGl2ID0gMHhjZmZmZmYgKH4wLjgxMjUgaW5zdGVhZCBvZgogIDB4YzAwMDAwID0gMC43NSks IHdoaWNoIGFkZHMgODEyLjUga0h6IGluc3RlYWQgb2YgNzUwIGtIeiBhbmQgcmVjYWxjdWxhdGVz CiAgdG8gMzM4MTIwMDAsIDc4ODEyMDAwLCA4NTgxMjAwMCwgODg4MTIwMDAsIDEzNjgxMjAwMCwg YW5kIDI2MjgxMjAwMCBIei4KCldoZW4gaGRtaV9wY2xrIGlzIHByZXBhcmVkIGFuZCBzdGFyZml2 ZV9oZG1pX3BoeV9jbGtfcmVjYWxjX3JhdGUoKSBydW5zOgoKICAgIGNsa19jaGFuZ2VfcmF0ZSgp CiAgICAgIGNsa19yZWNhbGMoKQogICAgICAgIHN0YXJmaXZlX2hkbWlfcGh5X2Nsa19yZWNhbGNf cmF0ZSgpCiAgICAgICAgICBpbm5vX2hkbWlfcGh5X3ByZV9wbGxfcmVjYWxjX3JhdGUoKQoKdGhl IGNsb2NrIGZyYW1ld29yayBjYWNoZXMgdGhlIHJlY2FsY3VsYXRlZCByYXRlIGluIGNvcmUtPnJh dGUuIFdoZW4Kc3RhcmZpdmVfaGRtaV9waHlfcG93ZXJfb24oKSB0aGVuIGNhbGxzOgoKICAgIHRt ZHNjbG9jayA9IGNsa19nZXRfcmF0ZShpbm5vLT5waHljbGspOwogICAgcHJlX2NmZyA9IGlubm9f aGRtaV9waHlfcHJlX3BsbF9sb29rdXAoJmlubm8tPnByZV9wbGwsIHRtZHNjbG9jaywKICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHRtZHNjbG9jayk7Cgppbm5vX2hk bWlfcGh5X3ByZV9wbGxfbG9va3VwKCkgcmVxdWlyZXMgYW4gZXhhY3QgbWF0Y2ggYWdhaW5zdApj ZmctPnBpeGNsb2NrIGluIHByZV9wbGxfY2ZnX3RhYmxlLCB3aGljaCBmYWlscyB3aXRoIC1FSU5W QUwgZm9yIGFsbCBlaWdodAptb2Rlcy4KClsgLi4uIF0KPiArc3RhdGljIGlubGluZSB2b2lkIGlu bm9fd3JpdGUoc3RydWN0IHN0YXJmaXZlX2hkbWlfcGh5ICppbm5vLCB1MzIgcmVnLCB1OCB2YWwp Cj4gK3sKPiArCXJlZ21hcF93cml0ZShpbm5vLT5yZWdtYXAsIHJlZyAqIDQsIHZhbCk7Cj4gK30K PiArCj4gK3N0YXRpYyBpbmxpbmUgdTggaW5ub19yZWFkKHN0cnVjdCBzdGFyZml2ZV9oZG1pX3Bo eSAqaW5ubywgdTMyIHJlZykKPiArewo+ICsJdTMyIHZhbDsKPiArCj4gKwlyZWdtYXBfcmVhZChp bm5vLT5yZWdtYXAsIHJlZyAqIDQsICZ2YWwpOwo+ICsJcmV0dXJuIHZhbDsKPiArfQoKW1NldmVy aXR5OiBMb3ddCklzIGlubm9fcmVhZCgpIG5lZWRlZCBoZXJlPyBJdCBpcyBuZXZlciBjYWxsZWQg aW4gdGhpcyBmaWxlLCBhbmQgdGhlCnJlZ2lzdGVyIGJpdCBtYWNyb3MgU1RGX0lOTk9fUE9TVF9Q TExfUE9TVF9ESVZfRU5BQkxFLApTVEZfSU5OT19QT1NUX1BMTF9SRUZDTEtfU0VMX1RNRFMsIFNU Rl9JTk5PX1BPU1RfUExMX0ZCX0RJVl84LApTVEZfSU5OT19QT1NUX1BMTF9GQl9ESVZfN18wLCBT VEZfSU5OT19QT1NUX1BMTF9QT1NUX0RJVl9NQVNLLCBhbmQKU1RGX0lOTk9fVE1EU19EUklWRVJf RU5BQkxFIGRlZmluZWQgYXQgdGhlIHRvcCBvZiB0aGUgZmlsZSBhcmUgYWxzbyB1bnVzZWQKKHdo aWxlIHN0YXJmaXZlX2hkbWlfcGh5X3Bvd2VyX29uKCkgb3Blbi1jb2RlcyAweDBlLCAweDAyLCBj ZmctPmZiZGl2ICYgMHhmZiwKYW5kIDB4OGYpLCB3aGljaCB0cmlnZ2VycyBjb21waWxlciB3YXJu aW5ncyB1bmRlciBXPTIgYnVpbGRzLgoKWyAuLi4gXQo+ICtzdGF0aWMgaW50IHN0YXJmaXZlX2hk bWlfcGh5X2Nsa19wcmVwYXJlKHN0cnVjdCBjbGtfaHcgKmh3KQo+ICt7Cj4gKwlzdHJ1Y3Qgc3Rh cmZpdmVfaGRtaV9waHkgKmlubm8gPSB0b19zdGFyZml2ZV9oZG1pX3BoeShodyk7Cj4gKwlpbnQg cmV0Owo+ICsKPiArCWlubm9faGRtaV9waHlfcHJlX3BsbF9wb3dlcl9kb3duKCZpbm5vLT5wcmVf cGxsLCBmYWxzZSk7Cj4gKwo+ICsJaWYgKGlubm9faGRtaV9waHlfcHJlX3BsbF9pc19sb2NrZWQo Jmlubm8tPnByZV9wbGwpKQo+ICsJCXJldHVybiAwOwo+ICsKPiArCXJldCA9IGlubm9faGRtaV9w aHlfcHJlX3BsbF93YWl0X2xvY2tlZCgmaW5uby0+cHJlX3BsbCwgMTAwMDAwKTsKPiArCWlmIChy ZXQpIHsKPiArCQlkZXZfZXJyKGlubm8tPmRldiwgIlRpbWVvdXQgd2FpdGluZyBmb3IgcHJlLVBM TCBsb2NrXG4iKTsKPiArCQlpbm5vX2hkbWlfcGh5X3ByZV9wbGxfcG93ZXJfZG93bigmaW5uby0+ cHJlX3BsbCwgdHJ1ZSk7Cj4gKwkJcmV0dXJuIHJldDsKPiArCX0KPiArCj4gKwlyZXR1cm4gMDsK PiArfQo+ICsKPiArc3RhdGljIHZvaWQgc3RhcmZpdmVfaGRtaV9waHlfY2xrX3VucHJlcGFyZShz dHJ1Y3QgY2xrX2h3ICpodykKPiArewo+ICsJc3RydWN0IHN0YXJmaXZlX2hkbWlfcGh5ICppbm5v ID0gdG9fc3RhcmZpdmVfaGRtaV9waHkoaHcpOwo+ICsKPiArCWlubm9faGRtaV9waHlfcHJlX3Bs bF9wb3dlcl9kb3duKCZpbm5vLT5wcmVfcGxsLCB0cnVlKTsKPiArCWlubm8tPnBpeGNsb2NrID0g MDsgLyogSW52YWxpZGF0ZSBjYWNoZWQgcmF0ZSAqLwo+ICt9Cj4gKwo+ICtzdGF0aWMgdW5zaWdu ZWQgbG9uZyBzdGFyZml2ZV9oZG1pX3BoeV9jbGtfcmVjYWxjX3JhdGUoc3RydWN0IGNsa19odyAq aHcsCj4gKwkJCQkJCSAgICAgICB1bnNpZ25lZCBsb25nIHBhcmVudF9yYXRlKQo+ICt7Cj4gKwlz dHJ1Y3Qgc3RhcmZpdmVfaGRtaV9waHkgKmlubm8gPSB0b19zdGFyZml2ZV9oZG1pX3BoeShodyk7 Cj4gKwo+ICsJLyoKPiArCSAqIFJlYWRpbmcgdGhlIFBMTCBiYWNrIHJlcXVpcmVzIHRoZSBIRE1J IGNvbnRyb2xsZXIncyBzeXN0ZW0gY2xvY2ssCj4gKwkgKiB3aGljaCB0aGUgc2libGluZyBjb250 cm9sbGVyIGRyaXZlciBob2xkcyBhbmQgdGhpcyBkcml2ZXIgY2Fubm90Cj4gKwkgKiByZXF1ZXN0 IHdpdGhvdXQgY3JlYXRpbmcgYSBwcm9iZSBjeWNsZSB3aXRoIHZvdXRjcmcuIFRoZSBjbG9jawo+ ICsJICogZnJhbWV3b3JrIHdhbGtzIGV2ZXJ5IHJlZ2lzdGVyZWQgY2xvY2sgcmVnYXJkbGVzcyBv ZiB3aGljaCBkcml2ZXJzCj4gKwkgKiBoYXZlIGJvdW5kLCBzbyBmYWxsIGJhY2sgdG8gdGhlIGNh Y2hlZCByYXRlIHdoZW5ldmVyIHRoaXMgY2xvY2sgaXMKPiArCSAqIG5vdCBwcmVwYXJlZDsgYW4g dW5jbG9ja2VkIGFjY2VzcyB0byB0aGUgc2hhcmVkIHJlZ2lzdGVyIHdpbmRvdwo+ICsJICogd2Vk Z2VzIHRoZSBidXMgaGFyZCBlbm91Z2ggdGhhdCB0aGUgQ1BVIHN0b3BzIHRha2luZyBOTUlzLgo+ ICsJICovCj4gKwlpZiAoIWNsa19od19pc19wcmVwYXJlZChodykpCj4gKwkJcmV0dXJuIGlubm8t PnBpeGNsb2NrOwo+ICsKPiArCWlubm8tPnBpeGNsb2NrID0gaW5ub19oZG1pX3BoeV9wcmVfcGxs X3JlY2FsY19yYXRlKCZpbm5vLT5wcmVfcGxsLAo+ICsJCQkJCQkJICAgcGFyZW50X3JhdGUpOwo+ ICsKPiArCXJldHVybiBpbm5vLT5waXhjbG9jazsKPiArfQpbIC4uLiBdCj4gK3N0YXRpYyBpbnQg c3RhcmZpdmVfaGRtaV9waHlfY2xrX3NldF9yYXRlKHN0cnVjdCBjbGtfaHcgKmh3LCB1bnNpZ25l ZCBsb25nIHJhdGUsCj4gKwkJCQkJICB1bnNpZ25lZCBsb25nIHBhcmVudF9yYXRlKQo+ICt7Cj4g KwlzdHJ1Y3Qgc3RhcmZpdmVfaGRtaV9waHkgKmlubm8gPSB0b19zdGFyZml2ZV9oZG1pX3BoeSho dyk7Cj4gKwljb25zdCBzdHJ1Y3QgaW5ub19oZG1pX3BoeV9wcmVfcGxsX2NvbmZpZyAqY2ZnOwo+ ICsKPiArCS8qCj4gKwkgKiBUaGUgSkg3MTEwIG9ubHkgZHJpdmVzIDhicGMsIHNvIHRoZSBUTURT IGNsb2NrIGFsd2F5cyBtYXRjaGVzIHRoZQo+ICsJICogcGl4ZWwgY2xvY2suCj4gKwkgKi8KPiAr CWNmZyA9IGlubm9faGRtaV9waHlfcHJlX3BsbF9sb29rdXAoJmlubm8tPnByZV9wbGwsIHJhdGUs IHJhdGUpOwo+ICsJaWYgKElTX0VSUihjZmcpKQo+ICsJCXJldHVybiBQVFJfRVJSKGNmZyk7Cj4g Kwo+ICsJZGV2X2RiZyhpbm5vLT5kZXYsICIlcyByYXRlICVsdSB0bWRzY2xrICVsdVxuIiwKPiAr CQlfX2Z1bmNfXywgcmF0ZSwgY2ZnLT50bWRzY2xvY2spOwo+ICsKPiArCWlmIChpbm5vLT5waXhj bG9jayA9PSByYXRlICYmIGlubm8tPnRtZHNjbG9jayA9PSBjZmctPnRtZHNjbG9jaykKPiArCQly ZXR1cm4gMDsKPiArCj4gKwlpbm5vX3VwZGF0ZV9iaXRzKGlubm8sIFNURl9JTk5PX0JJQVNfQ09O VFJPTCwKPiArCQkJIFNURl9JTk5PX0JJQVNfRU5BQkxFLCBTVEZfSU5OT19CSUFTX0VOQUJMRSk7 Cj4gKwlpbm5vX3dyaXRlKGlubm8sIFNURl9JTk5PX1JYX0NPTlRST0wsIFNURl9JTk5PX1JYX0VO QUJMRSk7Cj4gKwo+ICsJaW5ub19oZG1pX3BoeV9wcmVfcGxsX3Bvd2VyX2Rvd24oJmlubm8tPnBy ZV9wbGwsIHRydWUpOwo+ICsJaW5ub19oZG1pX3BoeV9wcmVfcGxsX2NvbmZpZ3VyZSgmaW5uby0+ cHJlX3BsbCwgY2ZnKTsKPiArCWlubm9faGRtaV9waHlfcHJlX3BsbF9wb3dlcl9kb3duKCZpbm5v LT5wcmVfcGxsLCBmYWxzZSk7Cj4gKwo+ICsJaW5uby0+cGl4Y2xvY2sgPSByYXRlOwo+ICsJaW5u by0+dG1kc2Nsb2NrID0gY2ZnLT50bWRzY2xvY2s7Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KCltT ZXZlcml0eTogTWVkaXVtXQpTaG91bGQgc3RhcmZpdmVfaGRtaV9waHlfY2xrX3NldF9yYXRlKCkg d2FpdCBmb3IgdGhlIFByZS1QTEwgdG8gbG9jayBvciBrZWVwCml0IHBvd2VyZWQgZG93biB3aGVu IHRoZSBjbG9jayBpcyB1bnByZXBhcmVkPwoKSW4gc3RhcmZpdmVfaGRtaV9waHlfY2xrX3NldF9y YXRlKCksIHRoZSBkcml2ZXIgcG93ZXJzIGRvd24gdGhlIFByZS1QTEwsCmNvbmZpZ3VyZXMgaXQs IGFuZCBwb3dlcnMgaXQgYmFjayB1cCB2aWEKaW5ub19oZG1pX3BoeV9wcmVfcGxsX3Bvd2VyX2Rv d24oJmlubm8tPnByZV9wbGwsIGZhbHNlKSwgcmV0dXJuaW5nIDAgd2l0aG91dApjYWxsaW5nIGlu bm9faGRtaV9waHlfcHJlX3BsbF93YWl0X2xvY2tlZCgpLgoKSWYgY2xrX3NldF9yYXRlKCkgaXMg Y2FsbGVkIHdoaWxlIGhkbWlfcGNsayBpcyBhbHJlYWR5IHByZXBhcmVkLApzdGFyZml2ZV9oZG1p X3BoeV9jbGtfcHJlcGFyZSgpIGlzIG5vdCBjYWxsZWQgYWdhaW4gYmVjYXVzZSBwcmVwYXJlX2Nv dW50IGlzCmFscmVhZHkgbm9uLXplcm8sIHNvIG5vdGhpbmcgd2FpdHMgZm9yIHRoZSBQcmUtUExM IHRvIGxvY2sgYmVmb3JlCnN0YXJmaXZlX2hkbWlfcGh5X3Bvd2VyX29uKCkgY29uZmlndXJlcyBh bmQgZW5hYmxlcyB0aGUgUG9zdC1QTEwgKHdoaWNoIHVzZXMKdGhlIFByZS1QTEwgVE1EUyBjbG9j ayBhcyBpdHMgcmVmZXJlbmNlKS4KCkNvbnZlcnNlbHksIGlmIGNsa19zZXRfcmF0ZSgpIGlzIGNh bGxlZCB3aGlsZSBoZG1pX3BjbGsgaXMgdW5wcmVwYXJlZCwKc3RhcmZpdmVfaGRtaV9waHlfY2xr X3NldF9yYXRlKCkgbGVhdmVzIHRoZSBQcmUtUExMLCBTVEZfSU5OT19CSUFTX0VOQUJMRSwKYW5k IFNURl9JTk5PX1JYX0VOQUJMRSBwb3dlcmVkIG9uIGluIGhhcmR3YXJlIHdoaWxlIHByZXBhcmVf Y291bnQgaXMgMC4KCj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGNsa19vcHMgc3RhcmZpdmVf aGRtaV9waHlfY2xrX29wcyA9IHsKPiArCS5wcmVwYXJlID0gc3RhcmZpdmVfaGRtaV9waHlfY2xr X3ByZXBhcmUsCj4gKwkudW5wcmVwYXJlID0gc3RhcmZpdmVfaGRtaV9waHlfY2xrX3VucHJlcGFy ZSwKPiArCS5yZWNhbGNfcmF0ZSA9IHN0YXJmaXZlX2hkbWlfcGh5X2Nsa19yZWNhbGNfcmF0ZSwK PiArCS5kZXRlcm1pbmVfcmF0ZSA9IHN0YXJmaXZlX2hkbWlfcGh5X2Nsa19kZXRlcm1pbmVfcmF0 ZSwKPiArCS5zZXRfcmF0ZSA9IHN0YXJmaXZlX2hkbWlfcGh5X2Nsa19zZXRfcmF0ZSwKPiArfTsK PiArCj4gK3N0YXRpYyB2b2lkIHN0YXJmaXZlX2hkbWlfcGh5X3Bvd2VyX2Rvd24oc3RydWN0IHN0 YXJmaXZlX2hkbWlfcGh5ICppbm5vKQo+ICt7Cj4gKwlpbm5vX3dyaXRlKGlubm8sIFNURl9JTk5P X1RNRFNfQ09OVFJPTCwgMHgwMCk7Cj4gKwlpbm5vX3dyaXRlKGlubm8sIFNURl9JTk5PX1NFUklB TElFUl9DT05UUk9MLCAweDAwKTsKPiArCWlubm9fd3JpdGUoaW5ubywgU1RGX0lOTk9fTERPX0NP TlRST0wsIDB4MDApOwo+ICsJaW5ub191cGRhdGVfYml0cyhpbm5vLCBTVEZfSU5OT19CSUFTX0NP TlRST0wsCj4gKwkJCSBTVEZfSU5OT19CSUFTX0VOQUJMRSwgMHgwMCk7Cj4gKwlpbm5vX3dyaXRl KGlubm8sIFNURl9JTk5PX1JYX0NPTlRST0wsIDB4MDApOwo+ICsKPiArCS8qIFBvd2VyIGRvd24g UG9zdC1QTEwgKi8KPiArCWlubm9fdXBkYXRlX2JpdHMoaW5ubywgU1RGX0lOTk9fUE9TVF9QTExf RElWXzEsCj4gKwkJCSBTVEZfSU5OT19QT1NUX1BMTF9QT1dFUl9ET1dOLAo+ICsJCQkgU1RGX0lO Tk9fUE9TVF9QTExfUE9XRVJfRE9XTik7Cj4gKwo+ICsJaW5uby0+dG1kc2Nsb2NrID0gMDsKPiAr CWlubm8tPnBpeGNsb2NrID0gMDsKPiArfQoKW1NldmVyaXR5OiBIaWdoXQpXaGF0IGhhcHBlbnMg d2hlbiBIRE1JIG91dHB1dCBpcyBkaXNhYmxlZCBhbmQgdGhlbiByZS1lbmFibGVkIGF0IHRoZSBz YW1lCnBpeGVsIGNsb2NrIHJhdGU/CgpXaGVuIHRoZSBkaXNwbGF5IGlzIGRpc2FibGVkOgoxLiBz dGFyZml2ZV9oZG1pX3BoeV9wb3dlcl9vZmYoKSAtPiBzdGFyZml2ZV9oZG1pX3BoeV9wb3dlcl9k b3duKCkgY2xlYXJzCiAgIFNURl9JTk5PX0JJQVNfRU5BQkxFIGFuZCBTVEZfSU5OT19SWF9DT05U Uk9MIHRvIDAsIGFuZCBzZXRzCiAgIGlubm8tPnRtZHNjbG9jayA9IDAgYW5kIGlubm8tPnBpeGNs b2NrID0gMC4KMi4gY2xrX2Rpc2FibGVfdW5wcmVwYXJlKCkgLT4gc3RhcmZpdmVfaGRtaV9waHlf Y2xrX3VucHJlcGFyZSgpIHBvd2VycyBkb3duCiAgIHRoZSBQcmUtUExMIGFuZCBzZXRzIGlubm8t PnBpeGNsb2NrID0gMC4KCkhvd2V2ZXIsIGNsa19jb3JlX3VucHJlcGFyZSgpIGluIHRoZSBjbG9j ayBmcmFtZXdvcmsgZG9lcyBub3QgY2xlYXIKY29yZS0+cmF0ZSwgc28gdGhlIGNsb2NrIGZyYW1l d29yayBzdGlsbCBjYWNoZXMgdGhlIHByZXZpb3VzIHJhdGUgUi4KCldoZW4gdGhlIGRpc3BsYXkg aXMgcmUtZW5hYmxlZCBhdCB0aGUgc2FtZSByYXRlIFI6CjEuIGNsa19zZXRfcmF0ZShwaHljbGss IFIpIHNlZXMgcmF0ZSA9PSBjbGtfY29yZV9nZXRfcmF0ZV9ub2xvY2soY29yZSkgaW4KICAgY2xr X2NvcmVfc2V0X3JhdGVfbm9sb2NrKCkgYW5kIHJldHVybnMgMCBlYXJseSB3aXRob3V0IGNhbGxp bmcKICAgc3RhcmZpdmVfaGRtaV9waHlfY2xrX3NldF9yYXRlKCkuCjIuIGNsa19wcmVwYXJlX2Vu YWJsZShwaHljbGspIGNhbGxzIHN0YXJmaXZlX2hkbWlfcGh5X2Nsa19wcmVwYXJlKCkgYmVmb3Jl CiAgIHBoeV9wb3dlcl9vbigpLCBwb3dlcmluZyB1cCB0aGUgUHJlLVBMTCBhbmQgcG9sbGluZwog ICBpbm5vX2hkbWlfcGh5X3ByZV9wbGxfd2FpdF9sb2NrZWQoKSB3aGlsZSBTVEZfSU5OT19CSUFT X0VOQUJMRSBhbmQKICAgU1RGX0lOTk9fUlhfRU5BQkxFIGFyZSBzdGlsbCBkaXNhYmxlZCBhdCAw IChhbmQgd2l0aG91dCByZXByb2dyYW1taW5nIHRoZQogICBQcmUtUExMIGlmIHRoZSBzaGFyZWQg cmVnaXN0ZXIgYmxvY2sgd2FzIHJlc2V0KS4KCkFkZGl0aW9uYWxseSwgaWYgYSBjbG9jayB0cmVl IHdhbGsgaW52b2tlcyBzdGFyZml2ZV9oZG1pX3BoeV9jbGtfcmVjYWxjX3JhdGUoKQp3aGlsZSBw aHljbGsgaXMgdW5wcmVwYXJlZCBhZnRlciBpbm5vLT5waXhjbG9jayB3YXMgemVyb2VkLCBpdCBy ZXR1cm5zIDAgYW5kCm92ZXJ3cml0ZXMgY29yZS0+cmF0ZSB3aXRoIDAuIElmIHRoZSBkaXNwbGF5 IGlzIHRoZW4gcmUtZW5hYmxlZCB3aXRob3V0IGEgbmV3CmNsa19zZXRfcmF0ZSgpIGNhbGwsIGNs a19nZXRfcmF0ZShpbm5vLT5waHljbGspIGluCnN0YXJmaXZlX2hkbWlfcGh5X3Bvd2VyX29uKCkg cmV0dXJucyAwIGFuZCBmYWlscwppbm5vX2hkbWlfcGh5X3ByZV9wbGxfbG9va3VwKCkgd2l0aCAt RUlOVkFMLgoKLS0gClNhc2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2FzaGlrby5kZXYvIy9w YXRjaHNldC8yMDI2MTAyOC1qaDcxMTAtaW5uby1oZG1pLXBoeS12Ni0wLWYzMzc5Njg0ZDk3ZUBz YW1zdW5nLmNvbT9wYXJ0PTQKCi0tIApsaW51eC1waHkgbWFpbGluZyBsaXN0CmxpbnV4LXBoeUBs aXN0cy5pbmZyYWRlYWQub3JnCmh0dHBzOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xp c3RpbmZvL2xpbnV4LXBoeQo=