From: sashiko-bot@kernel.org
To: "Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH v5 2/2] PCI: qcom: Add Nord PCIe controller support
Date: Thu, 29 Oct 2026 06:13:24 +0000 [thread overview]
Message-ID: <sashiko-outbox-188797@kernel.org> (raw)
In-Reply-To: <20261029-nord-v5-2-1a13c214e89d@oss.qualcomm.com>
> Add the Nord PCIe controller configuration and the platform-specific
> settings required for correct operation.
>
> Nord requires the NO_SNOOP override and L0s to be disabled. It also
> requires a clock-gating-control (CGC) workaround to address a PCIe
> power-domain timing-convergence issue. Set the CORE_CLK_CGC_DIS and
> AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
> The SLV_ACLK_CGC_DIS bit is already configured by hardware reset.
>
> This behavior is documented in the private QCTDD11972446 erratum,
> which is not publicly available.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-nord-v5-0-1a13c214e89d@oss.qualcomm.com?part=2
prev parent reply other threads:[~2026-10-29 6:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 6:10 [PATCH v5 0/2] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
2026-10-29 6:10 ` Krishna Chaitanya Chundru
2026-10-29 6:10 ` [PATCH v5 1/2] dt-bindings: pci: qcom: add Nord PCIe controller compatible Krishna Chaitanya Chundru
2026-10-29 6:10 ` Krishna Chaitanya Chundru
2026-10-29 6:12 ` sashiko-bot
2026-10-29 6:10 ` [PATCH v5 2/2] PCI: qcom: Add Nord PCIe controller support Krishna Chaitanya Chundru
2026-10-29 6:10 ` Krishna Chaitanya Chundru
2026-10-29 6:13 ` sashiko-bot [this message]
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