From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793267828; b=C1jZ3yAQorqMTfgpvkzYwPcdkV53jRLGyT5OkvE5IgFYFpYZG0rzT77oMHpzoFcGPKsN HIfoaJx7EAOBnKYHWMtodr2tgy8NW+OYlczp1tyR+EXNUiNMpKaR/Ar+A6cjmUxp6aXWa B+6bNzS5mW3QDZsU5//UhZWN2Egk0hqBCxgYUM2wh9JDmYlUrE2G1MZtImy7nPqoDWM21 6xTKB8u0ehLUfrpznjmoLMDyZf9jqtlNJD9IyjWf4VQko6Mf6fsi6qBxTUseyTR/tmf3t dK3p4mL5aRjd2Z7EyQ7F9Dfs0dv33ZkFLI1FNzSgs4if5DNOrpUFaYNihHLX2n9u/cQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793267828; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=FL2eR8EYUTXDFliIvq3+r6VI7BGzi6yXCZSbMiEvJYo=; b=B8AqCK1YcR3EnJOP31e0578mTJaStNoGb6P3qSIKr2KLRESXK4+vQ1w0Rev3Knf8kmXl h142r1Cxx28v+DbnUrIgkRRJ/flsptaI/ALo9sujPWjc80zMhN0K2gJY/AX+0FzUOEbZb ltr6sRmSxS+6TGhZcIJ3ujVEQ2D+3SFeI1HmI4vnOcF6XNHm9hNrWKz4yZV4pMw/Nez4Q iw5QKaPaB6KMn2NaoH72KfzZLcdouNOMY+PDcNyfQspvMy1klf4E5xkGtKbRJE2l6yGR7 wTW0KDCUcRpRujgkQiD2mvM2FbbM0tz+jvnOgwnu1g+TCcjtTo1o7/nH46/EU6DC3ag== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=VfeDA2nt; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 458B2606A33A; Thu, 29 Oct 2026 09:57:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=VfeDA2nt Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DFDA1F01829; Thu, 29 Oct 2026 09:57:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793267828; bh=FL2eR8EYUTXDFliIvq3+r6VI7BGzi6yXCZSbMiEvJYo=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=VfeDA2ntD2A6A8rVIMHLYdB0UD35qsrcpyzddVxVd3eziYxFDYS6KsSG4gmR9DSUU yQEekc0zu8o/YdXb+xpL1oYtBRhQblENp7EpQ9CsiP/dWLwNqHvtaj8NHh6+rCTpbz 0nomhn026dGIzHyV4+Lq3thfTvCIAVvRoidmh4xGqcbdkQer8ewjLGO3Hj+hJJhqwk n8gUV/7+ehMOPQIKMe5aIrcdmZSvPJrLwLbAKC3lnGaVY39XnKtMOzas4wSxsfLumN CAb0LCXy+FIFsqpWtlCqH8AF7XrQuMsVRn7vNY/zV8DNVr70/HCtx7KEFBWetMuVe9 wsj8nA2C02D2w== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH RFC RFT v2 3/3] clk: meson: pll: Remove the dedicated n parameter Reply-To: sashiko-reviews@lists.linux.dev To: "Jian Hu" Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org In-Reply-To: <20261029-meson_refactor_n-v2-3-ff4ac74e527b@amlogic.com> References: <20261029-meson_refactor_n-v2-0-ff4ac74e527b@amlogic.com> <20261029-meson_refactor_n-v2-3-ff4ac74e527b@amlogic.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Thu, 29 Oct 2026 09:57:07 +0000 X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 4 potential issue(= s) to consider: - [High] clk: meson: pll: CLK_SET_RATE_PARENT on ro_ops PLL DCOs breaks rat= e rounding - [High] clk: meson: pll: meson_clk_get_pll_table() fails on non-exact mult= ipliers - [High] clk: meson: meson8b: missing CLK_SET_RATE_PARENT on hdmi_pll_dco_in - [High] clk: meson: pll: cached 0 Hz pre-divider rate on directly programm= ed PLLs -- commit b0439d678a94dfead2cca909902c6363ae03f5d0 Author: Jian Hu clk: meson: pll: Remove the dedicated n parameter This commit removes the dedicated pre-divider (n) field from struct meson_clk_pll_data and simplifies the Meson PLL rate calculation. Each PLL pre-divider is instead modeled as a standalone divider clock that serves as the parent of the PLL DCO clock. > diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c > index 280842e9cb371..e6e6b9a8030c0 100644 > --- a/drivers/clk/meson/axg.c > +++ b/drivers/clk/meson/axg.c [ ... ] > @@ -202,10 +240,11 @@ static struct clk_regmap axg_sys_pll_dco =3D { > .hw.init =3D &(struct clk_init_data){ > .name =3D "sys_pll_dco", > .ops =3D &meson_clk_pll_ro_ops, > - .parent_data =3D &(const struct clk_parent_data) { > - .fw_name =3D "xtal", > + .parent_hws =3D (const struct clk_hw *[]) { > + &axg_sys_prediv.hw > }, > .num_parents =3D 1, > + .flags =3D CLK_SET_RATE_PARENT, > }, > }; [Severity: High] Does setting CLK_SET_RATE_PARENT on a clock using meson_clk_pll_ro_ops break rate rounding and rate calculation in the common clock framework? meson_clk_pll_ro_ops only provides .init, .recalc_rate, and .is_enabled, and does not implement .determine_rate or .round_rate, so clk_core_can_round() = is false. In drivers/clk/clk.c, clk_core_round_rate_nolock() checks: if (clk_core_can_round(core)) return core->ops->determine_rate(core->hw, req); else if (core->flags & CLK_SET_RATE_PARENT) return clk_core_round_rate_nolock(core->parent, req); When CLK_SET_RATE_PARENT is set on a clock that cannot round its own rate, clk_core_round_rate_nolock() and clk_calc_new_rates() treat the clock as a 1:1 pass-through of its parent and set the rate to the parent pre-divider rate (24 MHz or 48 MHz) instead of the multi-GHz DCO frequency. This affects child dividers with CLK_SET_RATE_PARENT when consumer drivers call clk_round_rate() or clk_set_rate(). The same pattern is also added on: - sm1_gp1_pll_dco and g12a_hdmi_pll_dco in drivers/clk/meson/g12a.c - gxbb_hdmi_pll_dco, gxl_hdmi_pll_dco, and gxbb_sys_pll_dco in drivers/clk/meson/gxbb.c - s4_fixed_pll_dco in drivers/clk/meson/s4-pll.c Should these meson_clk_pll_ro_ops DCO clocks omit CLK_SET_RATE_PARENT (and use clk_regmap_divider_ro_ops for their pre-dividers)? > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c > index 1ea6579a760f3..a7e3f8c8eb783 100644 > --- a/drivers/clk/meson/clk-pll.c > +++ b/drivers/clk/meson/clk-pll.c [ ... ] > +static int meson_clk_get_pll_table(unsigned long rate, > + unsigned long parent_rate, > + unsigned int *m, > + struct meson_clk_pll_data *pll) > +{ > + unsigned int i; > + int ret; > + > + for (i =3D 0, ret =3D 0; !ret; i++) { > + if (!pll->table[i].m) > + return -EINVAL; > + > + if (pll->table[i].m =3D=3D rate / parent_rate) { > + *m =3D pll->table[i].m; > + return 0; > + } > + } > + > + return 0; > +} [Severity: High] What happens in meson_clk_get_pll_table() when rate / parent_rate does not exactly match an entry in pll->table? Previously, meson_clk_get_pll_settings() iterated over pll->table and used meson_clk_pll_is_better() to pick either the closest entry (when __pll_round_closest_mult(pll) was true) or the largest table entry with a rate less than or equal to the requested rate. With this change, meson_clk_get_pll_table() requires an exact match for rate / parent_rate and returns -EINVAL otherwise: 1. Sparse multiplier tables such as sys_pll_params_table (which has a gap between m =3D 68 and m =3D 84 where Meson8 CPU OPPs at 1800 MHz and 1992= MHz fall) and meson8b_hdmi_pll_params_table in drivers/clk/meson/meson8b.c will fail with -EINVAL in meson_clk_pll_determine_rate() and meson_clk_pll_set_rate() when rate / parent_rate lands in a gap. 2. Unlike meson_clk_get_pll_range(), which clamps to min and max and returns -ENODATA, meson_clk_get_pll_table() returns -EINVAL when rate / parent_r= ate is below the minimum or above the maximum multiplier in the table. When a child post-divider runs clk_divider_bestdiv(), any candidate rate * i outside the table range fails, and the fallback clk_hw_round_rate(parent= , 1) also fails with -EINVAL because 1 / parent_rate is 0, causing clk_round_rate() to return 0 Hz. 3. meson_clk_get_pll_table() no longer checks __pll_round_closest_mult(pll) (for example on axg_hifi_pll_dco when fractional mode is not used), and leaves ret unmodified in the loop with an unreachable return 0 at the en= d. Should meson_clk_get_pll_table() retain the best-match and clamping behavior from meson_clk_get_pll_settings()? > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index bc029c6ab622d..0c9ba079bc51a 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c [ ... ] > @@ -185,15 +209,38 @@ static struct clk_regmap meson8b_fixed_pll =3D { > }, > }; > =20 > +static const struct clk_div_table meson8b_prediv_div_table[] =3D { > + { .val =3D 1, .div =3D 1 }, > + { /* sentinel */ } > +}; > + > +static struct clk_regmap meson8b_hdmi_prediv =3D { > + .data =3D &(struct clk_regmap_div_data){ > + .offset =3D HHI_VID_PLL_CNTL, > + .shift =3D 10, > + .width =3D 5, > + .table =3D meson8b_prediv_div_table, > + .flags =3D CLK_DIVIDER_INVALID_ZERO, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "hdmi_prediv", > + .ops =3D &clk_regmap_divider_ops, > + .parent_data =3D &(const struct clk_parent_data) { > + .fw_name =3D "xtal", > + .index =3D -1, > + }, > + .num_parents =3D 1, > + }, > +}; > + > static struct clk_fixed_factor hdmi_pll_dco_in =3D { > .mult =3D 2, > .div =3D 1, > .hw.init =3D &(struct clk_init_data){ > .name =3D "hdmi_pll_dco_in", > .ops =3D &clk_fixed_factor_ops, > - .parent_data =3D &(const struct clk_parent_data) { > - .fw_name =3D "xtal", > - .index =3D -1, > + .parent_hws =3D (const struct clk_hw *[]) { > + &meson8b_hdmi_prediv.hw > }, > .num_parents =3D 1, > }, [ ... ] > @@ -279,6 +321,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco =3D { > &hdmi_pll_dco_in.hw > }, > .num_parents =3D 1, > + .flags =3D CLK_SET_RATE_PARENT, > }, > }; [Severity: High] Can rate requests from meson8b_hdmi_pll_dco reach meson8b_hdmi_prediv witho= ut CLK_SET_RATE_PARENT on hdmi_pll_dco_in? meson8b_hdmi_pll_dco has hdmi_pll_dco_in as its parent, and hdmi_pll_dco_in has meson8b_hdmi_prediv as its parent: meson8b_hdmi_prediv -> hdmi_pll_dco_in -> meson8b_hdmi_pll_dco Because hdmi_pll_dco_in does not set CLK_SET_RATE_PARENT, when meson8b_hdmi_prediv resets to 0 and reports a 0 Hz rate via CLK_DIVIDER_INVALID_ZERO, meson_clk_pll_determine_rate() calls clk_hw_round_rate() on hdmi_pll_dco_in, and clk_factor_determine_rate() returns 0 without rounding meson8b_hdmi_prediv. This causes meson_clk_pll_determine_rate() to return -EINVAL and prevents clk_calc_new_rates() from propagating rate changes to program meson8b_hdmi_prediv. Should hdmi_pll_dco_in also have .flags =3D CLK_SET_RATE_PARENT? > diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c > index 0a622f45fa368..28d563fcb1bd2 100644 > --- a/drivers/clk/meson/t7-pll.c > +++ b/drivers/clk/meson/t7-pll.c [ ... ] > @@ -292,6 +346,24 @@ static struct clk_regmap t7_hifi_pll =3D { > }, > }; > =20 > +static struct clk_regmap t7_pcie_prediv =3D { > + .data =3D &(struct clk_regmap_div_data){ > + .offset =3D PCIEPLL_CTRL0, > + .shift =3D 10, > + .width =3D 5, > + .table =3D t7_prediv_div_table, > + .flags =3D CLK_DIVIDER_INVALID_ZERO, > + }, > + .hw.init =3D &(struct clk_init_data) { > + .name =3D "pcie_prediv", > + .ops =3D &clk_regmap_divider_ops, > + .parent_data =3D &(const struct clk_parent_data) { > + .fw_name =3D "in0", > + }, > + .num_parents =3D 1, > + }, > +}; [ ... ] > @@ -345,10 +412,11 @@ static struct clk_regmap t7_pcie_pll_dco =3D { > .hw.init =3D &(struct clk_init_data){ > .name =3D "pcie_pll_dco", > .ops =3D &meson_clk_pcie_pll_ops, > - .parent_data =3D &(const struct clk_parent_data) { > - .fw_name =3D "in0", > + .parent_hws =3D (const struct clk_hw *[]) { > + &t7_pcie_prediv.hw > }, > .num_parents =3D 1, > + .flags =3D CLK_SET_RATE_PARENT, > }, > }; [Severity: High] Will t7_pcie_prediv (as well as g12a_hdmi_prediv, gxbb_hdmi_prediv, and gxl_hdmi_prediv) remain stuck at a cached rate of 0 Hz if the hardware pre-divider field is 0 at clock registration time? t7_pcie_pll_dco uses meson_clk_pcie_pll_ops and defines neither .table nor .range; it only programs PCIEPLL_CTRL0 (including N =3D 1) inside meson_clk_pcie_pll_enable(). If PCIEPLL_CTRL0 has N =3D 0 at registration, t7_pcie_prediv caches a rate of 0 Hz via CLK_DIVIDER_INVALID_ZERO. Because clk_set_rate() cannot be used on t7_pcie_pll_dco (meson_clk_get_pll_max_mul= tiplier() returns 0 when neither .range nor .table is set) and t7_pcie_prediv does not have CLK_GET_RATE_NOCACHE, t7_pcie_prediv->rate is never recalculated after meson_clk_pcie_pll_enable() writes PCIEPLL_CTRL0. Similarly, in drivers/clk/meson/g12a.c (g12a_hdmi_prediv) and drivers/clk/meson/gxbb.c (gxbb_hdmi_prediv and gxl_hdmi_prediv), the HDMI P= LL registers are written directly by the DRM driver in drivers/gpu/drm/meson/meson_vclk.c rather than through clk_set_rate(). While hdmi_pll_dco has CLK_GET_RATE_NOCACHE, clk_core_get_rate_recalc() only recalculates downward from the clock with CLK_GET_RATE_NOCACHE using core->parent->rate. Because the parent hdmi_prediv clocks lack CLK_GET_RATE_NOCACHE, their cached rate stays 0 Hz even after the display driver programs N =3D 1, causing meson_clk_pll_recalc_rate() on hdmi_pll_dc= o to return 0 Hz. Should pre-dividers whose registers are programmed outside clk_set_rate() be marked with CLK_GET_RATE_NOCACHE? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261029-meson_refa= ctor_n-v2-0-ff4ac74e527b@amlogic.com?part=3D3 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21E91606A320 for ; Thu, 29 Oct 2026 09:57:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=B2g9Ik67; dkim=fail reason="signature verification failed" (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 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n8gUV/7+ehMOPQIKMe5aIrcdmZSvPJrLwLbAKC3lnGaVY39XnKtMOzas4wSxsfLumN CAb0LCXy+FIFsqpWtlCqH8AF7XrQuMsVRn7vNY/zV8DNVr70/HCtx7KEFBWetMuVe9 wsj8nA2C02D2w== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH RFC RFT v2 3/3] clk: meson: pll: Remove the dedicated n parameter To: "Jian Hu" Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org In-Reply-To: <20261029-meson_refactor_n-v2-3-ff4ac74e527b@amlogic.com> References: <20261029-meson_refactor_n-v2-0-ff4ac74e527b@amlogic.com> <20261029-meson_refactor_n-v2-3-ff4ac74e527b@amlogic.com> Date: Thu, 29 Oct 2026 09:57:07 +0000 X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-amlogic" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg NCBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIGNsazogbWVzb246IHBs bDogQ0xLX1NFVF9SQVRFX1BBUkVOVCBvbiByb19vcHMgUExMIERDT3MgYnJlYWtzIHJhdGUgcm91 bmRpbmcKLSBbSGlnaF0gY2xrOiBtZXNvbjogcGxsOiBtZXNvbl9jbGtfZ2V0X3BsbF90YWJsZSgp IGZhaWxzIG9uIG5vbi1leGFjdCBtdWx0aXBsaWVycwotIFtIaWdoXSBjbGs6IG1lc29uOiBtZXNv bjhiOiBtaXNzaW5nIENMS19TRVRfUkFURV9QQVJFTlQgb24gaGRtaV9wbGxfZGNvX2luCi0gW0hp Z2hdIGNsazogbWVzb246IHBsbDogY2FjaGVkIDAgSHogcHJlLWRpdmlkZXIgcmF0ZSBvbiBkaXJl Y3RseSBwcm9ncmFtbWVkIFBMTHMKLS0KCmNvbW1pdCBiMDQzOWQ2NzhhOTRkZmVhZDJjY2E5MDk5 MDJjNjM2M2FlMDNmNWQwCkF1dGhvcjogSmlhbiBIdSA8amlhbi5odUBhbWxvZ2ljLmNvbT4KCmNs azogbWVzb246IHBsbDogUmVtb3ZlIHRoZSBkZWRpY2F0ZWQgbiBwYXJhbWV0ZXIKClRoaXMgY29t bWl0IHJlbW92ZXMgdGhlIGRlZGljYXRlZCBwcmUtZGl2aWRlciAobikgZmllbGQgZnJvbQpzdHJ1 Y3QgbWVzb25fY2xrX3BsbF9kYXRhIGFuZCBzaW1wbGlmaWVzIHRoZSBNZXNvbiBQTEwgcmF0ZSBj YWxjdWxhdGlvbi4KRWFjaCBQTEwgcHJlLWRpdmlkZXIgaXMgaW5zdGVhZCBtb2RlbGVkIGFzIGEg c3RhbmRhbG9uZSBkaXZpZGVyIGNsb2NrIHRoYXQKc2VydmVzIGFzIHRoZSBwYXJlbnQgb2YgdGhl IFBMTCBEQ08gY2xvY2suCgo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Nsay9tZXNvbi9heGcuYyBi L2RyaXZlcnMvY2xrL21lc29uL2F4Zy5jCj4gaW5kZXggMjgwODQyZTljYjM3MS4uZTZlNmI5YTgw MzBjMCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2Nsay9tZXNvbi9heGcuYwo+ICsrKyBiL2RyaXZl cnMvY2xrL21lc29uL2F4Zy5jCgpbIC4uLiBdCgo+IEBAIC0yMDIsMTAgKzI0MCwxMSBAQCBzdGF0 aWMgc3RydWN0IGNsa19yZWdtYXAgYXhnX3N5c19wbGxfZGNvID0gewo+ICAJLmh3LmluaXQgPSAm KHN0cnVjdCBjbGtfaW5pdF9kYXRhKXsKPiAgCQkubmFtZSA9ICJzeXNfcGxsX2RjbyIsCj4gIAkJ Lm9wcyA9ICZtZXNvbl9jbGtfcGxsX3JvX29wcywKPiAtCQkucGFyZW50X2RhdGEgPSAmKGNvbnN0 IHN0cnVjdCBjbGtfcGFyZW50X2RhdGEpIHsKPiAtCQkJLmZ3X25hbWUgPSAieHRhbCIsCj4gKwkJ LnBhcmVudF9od3MgPSAoY29uc3Qgc3RydWN0IGNsa19odyAqW10pIHsKPiArCQkJJmF4Z19zeXNf cHJlZGl2Lmh3Cj4gIAkJfSwKPiAgCQkubnVtX3BhcmVudHMgPSAxLAo+ICsJCS5mbGFncyA9IENM S19TRVRfUkFURV9QQVJFTlQsCj4gIAl9LAo+ICB9OwoKW1NldmVyaXR5OiBIaWdoXQpEb2VzIHNl dHRpbmcgQ0xLX1NFVF9SQVRFX1BBUkVOVCBvbiBhIGNsb2NrIHVzaW5nIG1lc29uX2Nsa19wbGxf cm9fb3BzIGJyZWFrCnJhdGUgcm91bmRpbmcgYW5kIHJhdGUgY2FsY3VsYXRpb24gaW4gdGhlIGNv bW1vbiBjbG9jayBmcmFtZXdvcms/CgptZXNvbl9jbGtfcGxsX3JvX29wcyBvbmx5IHByb3ZpZGVz IC5pbml0LCAucmVjYWxjX3JhdGUsIGFuZCAuaXNfZW5hYmxlZCwgYW5kCmRvZXMgbm90IGltcGxl bWVudCAuZGV0ZXJtaW5lX3JhdGUgb3IgLnJvdW5kX3JhdGUsIHNvIGNsa19jb3JlX2Nhbl9yb3Vu ZCgpIGlzCmZhbHNlLgoKSW4gZHJpdmVycy9jbGsvY2xrLmMsIGNsa19jb3JlX3JvdW5kX3JhdGVf bm9sb2NrKCkgY2hlY2tzOgoKCWlmIChjbGtfY29yZV9jYW5fcm91bmQoY29yZSkpCgkJcmV0dXJu IGNvcmUtPm9wcy0+ZGV0ZXJtaW5lX3JhdGUoY29yZS0+aHcsIHJlcSk7CgllbHNlIGlmIChjb3Jl LT5mbGFncyAmIENMS19TRVRfUkFURV9QQVJFTlQpCgkJcmV0dXJuIGNsa19jb3JlX3JvdW5kX3Jh dGVfbm9sb2NrKGNvcmUtPnBhcmVudCwgcmVxKTsKCldoZW4gQ0xLX1NFVF9SQVRFX1BBUkVOVCBp cyBzZXQgb24gYSBjbG9jayB0aGF0IGNhbm5vdCByb3VuZCBpdHMgb3duIHJhdGUsCmNsa19jb3Jl X3JvdW5kX3JhdGVfbm9sb2NrKCkgYW5kIGNsa19jYWxjX25ld19yYXRlcygpIHRyZWF0IHRoZSBj bG9jayBhcyBhCjE6MSBwYXNzLXRocm91Z2ggb2YgaXRzIHBhcmVudCBhbmQgc2V0IHRoZSByYXRl IHRvIHRoZSBwYXJlbnQgcHJlLWRpdmlkZXIKcmF0ZSAoMjQgTUh6IG9yIDQ4IE1IeikgaW5zdGVh ZCBvZiB0aGUgbXVsdGktR0h6IERDTyBmcmVxdWVuY3kuCgpUaGlzIGFmZmVjdHMgY2hpbGQgZGl2 aWRlcnMgd2l0aCBDTEtfU0VUX1JBVEVfUEFSRU5UIHdoZW4gY29uc3VtZXIgZHJpdmVycwpjYWxs IGNsa19yb3VuZF9yYXRlKCkgb3IgY2xrX3NldF9yYXRlKCkuIFRoZSBzYW1lIHBhdHRlcm4gaXMg YWxzbyBhZGRlZCBvbjoKCiAgLSBzbTFfZ3AxX3BsbF9kY28gYW5kIGcxMmFfaGRtaV9wbGxfZGNv IGluIGRyaXZlcnMvY2xrL21lc29uL2cxMmEuYwogIC0gZ3hiYl9oZG1pX3BsbF9kY28sIGd4bF9o ZG1pX3BsbF9kY28sIGFuZCBneGJiX3N5c19wbGxfZGNvIGluCiAgICBkcml2ZXJzL2Nsay9tZXNv bi9neGJiLmMKICAtIHM0X2ZpeGVkX3BsbF9kY28gaW4gZHJpdmVycy9jbGsvbWVzb24vczQtcGxs LmMKClNob3VsZCB0aGVzZSBtZXNvbl9jbGtfcGxsX3JvX29wcyBEQ08gY2xvY2tzIG9taXQgQ0xL X1NFVF9SQVRFX1BBUkVOVCAoYW5kCnVzZSBjbGtfcmVnbWFwX2RpdmlkZXJfcm9fb3BzIGZvciB0 aGVpciBwcmUtZGl2aWRlcnMpPwoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9jbGsvbWVzb24vY2xr LXBsbC5jIGIvZHJpdmVycy9jbGsvbWVzb24vY2xrLXBsbC5jCj4gaW5kZXggMWVhNjU3OWE3NjBm My4uYTdlM2Y4YzhlYjc4MyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2Nsay9tZXNvbi9jbGstcGxs LmMKPiArKysgYi9kcml2ZXJzL2Nsay9tZXNvbi9jbGstcGxsLmMKClsgLi4uIF0KCj4gK3N0YXRp YyBpbnQgbWVzb25fY2xrX2dldF9wbGxfdGFibGUodW5zaWduZWQgbG9uZyByYXRlLAo+ICsJCQkJ ICAgdW5zaWduZWQgbG9uZyBwYXJlbnRfcmF0ZSwKPiArCQkJCSAgIHVuc2lnbmVkIGludCAqbSwK PiArCQkJCSAgIHN0cnVjdCBtZXNvbl9jbGtfcGxsX2RhdGEgKnBsbCkKPiArewo+ICsJdW5zaWdu ZWQgaW50IGk7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCWZvciAoaSA9IDAsIHJldCA9IDA7ICFyZXQ7 IGkrKykgewo+ICsJCWlmICghcGxsLT50YWJsZVtpXS5tKQo+ICsJCQlyZXR1cm4gLUVJTlZBTDsK PiArCj4gKwkJaWYgKHBsbC0+dGFibGVbaV0ubSA9PSByYXRlIC8gcGFyZW50X3JhdGUpIHsKPiAr CQkJKm0gPSBwbGwtPnRhYmxlW2ldLm07Cj4gKwkJCXJldHVybiAwOwo+ICsJCX0KPiArCX0KPiAr Cj4gKwlyZXR1cm4gMDsKPiArfQoKW1NldmVyaXR5OiBIaWdoXQpXaGF0IGhhcHBlbnMgaW4gbWVz b25fY2xrX2dldF9wbGxfdGFibGUoKSB3aGVuIHJhdGUgLyBwYXJlbnRfcmF0ZSBkb2VzIG5vdApl eGFjdGx5IG1hdGNoIGFuIGVudHJ5IGluIHBsbC0+dGFibGU/CgpQcmV2aW91c2x5LCBtZXNvbl9j bGtfZ2V0X3BsbF9zZXR0aW5ncygpIGl0ZXJhdGVkIG92ZXIgcGxsLT50YWJsZSBhbmQgdXNlZApt ZXNvbl9jbGtfcGxsX2lzX2JldHRlcigpIHRvIHBpY2sgZWl0aGVyIHRoZSBjbG9zZXN0IGVudHJ5 ICh3aGVuCl9fcGxsX3JvdW5kX2Nsb3Nlc3RfbXVsdChwbGwpIHdhcyB0cnVlKSBvciB0aGUgbGFy Z2VzdCB0YWJsZSBlbnRyeSB3aXRoIGEKcmF0ZSBsZXNzIHRoYW4gb3IgZXF1YWwgdG8gdGhlIHJl cXVlc3RlZCByYXRlLgoKV2l0aCB0aGlzIGNoYW5nZSwgbWVzb25fY2xrX2dldF9wbGxfdGFibGUo KSByZXF1aXJlcyBhbiBleGFjdCBtYXRjaCBmb3IKcmF0ZSAvIHBhcmVudF9yYXRlIGFuZCByZXR1 cm5zIC1FSU5WQUwgb3RoZXJ3aXNlOgoKMS4gU3BhcnNlIG11bHRpcGxpZXIgdGFibGVzIHN1Y2gg YXMgc3lzX3BsbF9wYXJhbXNfdGFibGUgKHdoaWNoIGhhcyBhIGdhcAogICBiZXR3ZWVuIG0gPSA2 OCBhbmQgbSA9IDg0IHdoZXJlIE1lc29uOCBDUFUgT1BQcyBhdCAxODAwIE1IeiBhbmQgMTk5MiBN SHoKICAgZmFsbCkgYW5kIG1lc29uOGJfaGRtaV9wbGxfcGFyYW1zX3RhYmxlIGluIGRyaXZlcnMv Y2xrL21lc29uL21lc29uOGIuYwogICB3aWxsIGZhaWwgd2l0aCAtRUlOVkFMIGluIG1lc29uX2Ns a19wbGxfZGV0ZXJtaW5lX3JhdGUoKSBhbmQKICAgbWVzb25fY2xrX3BsbF9zZXRfcmF0ZSgpIHdo ZW4gcmF0ZSAvIHBhcmVudF9yYXRlIGxhbmRzIGluIGEgZ2FwLgoKMi4gVW5saWtlIG1lc29uX2Ns a19nZXRfcGxsX3JhbmdlKCksIHdoaWNoIGNsYW1wcyB0byBtaW4gYW5kIG1heCBhbmQgcmV0dXJu cwogICAtRU5PREFUQSwgbWVzb25fY2xrX2dldF9wbGxfdGFibGUoKSByZXR1cm5zIC1FSU5WQUwg d2hlbiByYXRlIC8gcGFyZW50X3JhdGUKICAgaXMgYmVsb3cgdGhlIG1pbmltdW0gb3IgYWJvdmUg dGhlIG1heGltdW0gbXVsdGlwbGllciBpbiB0aGUgdGFibGUuIFdoZW4gYQogICBjaGlsZCBwb3N0 LWRpdmlkZXIgcnVucyBjbGtfZGl2aWRlcl9iZXN0ZGl2KCksIGFueSBjYW5kaWRhdGUgcmF0ZSAq IGkKICAgb3V0c2lkZSB0aGUgdGFibGUgcmFuZ2UgZmFpbHMsIGFuZCB0aGUgZmFsbGJhY2sgY2xr X2h3X3JvdW5kX3JhdGUocGFyZW50LCAxKQogICBhbHNvIGZhaWxzIHdpdGggLUVJTlZBTCBiZWNh dXNlIDEgLyBwYXJlbnRfcmF0ZSBpcyAwLCBjYXVzaW5nCiAgIGNsa19yb3VuZF9yYXRlKCkgdG8g cmV0dXJuIDAgSHouCgozLiBtZXNvbl9jbGtfZ2V0X3BsbF90YWJsZSgpIG5vIGxvbmdlciBjaGVj a3MgX19wbGxfcm91bmRfY2xvc2VzdF9tdWx0KHBsbCkKICAgKGZvciBleGFtcGxlIG9uIGF4Z19o aWZpX3BsbF9kY28gd2hlbiBmcmFjdGlvbmFsIG1vZGUgaXMgbm90IHVzZWQpLCBhbmQKICAgbGVh dmVzIHJldCB1bm1vZGlmaWVkIGluIHRoZSBsb29wIHdpdGggYW4gdW5yZWFjaGFibGUgcmV0dXJu IDAgYXQgdGhlIGVuZC4KClNob3VsZCBtZXNvbl9jbGtfZ2V0X3BsbF90YWJsZSgpIHJldGFpbiB0 aGUgYmVzdC1tYXRjaCBhbmQgY2xhbXBpbmcgYmVoYXZpb3IKZnJvbSBtZXNvbl9jbGtfZ2V0X3Bs bF9zZXR0aW5ncygpPwoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9jbGsvbWVzb24vbWVzb244Yi5j IGIvZHJpdmVycy9jbGsvbWVzb24vbWVzb244Yi5jCj4gaW5kZXggYmMwMjljNmFiNjIyZC4uMGM5 YmEwNzliYzUxYSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2Nsay9tZXNvbi9tZXNvbjhiLmMKPiAr KysgYi9kcml2ZXJzL2Nsay9tZXNvbi9tZXNvbjhiLmMKClsgLi4uIF0KCj4gQEAgLTE4NSwxNSAr MjA5LDM4IEBAIHN0YXRpYyBzdHJ1Y3QgY2xrX3JlZ21hcCBtZXNvbjhiX2ZpeGVkX3BsbCA9IHsK PiAgCX0sCj4gIH07Cj4gIAo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGNsa19kaXZfdGFibGUgbWVz b244Yl9wcmVkaXZfZGl2X3RhYmxlW10gPSB7Cj4gKwl7IC52YWwgPSAxLCAuZGl2ID0gMSB9LAo+ ICsJeyAvKiBzZW50aW5lbCAqLyB9Cj4gK307Cj4gKwo+ICtzdGF0aWMgc3RydWN0IGNsa19yZWdt YXAgbWVzb244Yl9oZG1pX3ByZWRpdiA9IHsKPiArCS5kYXRhID0gJihzdHJ1Y3QgY2xrX3JlZ21h cF9kaXZfZGF0YSl7Cj4gKwkJLm9mZnNldCA9IEhISV9WSURfUExMX0NOVEwsCj4gKwkJLnNoaWZ0 ICAgPSAxMCwKPiArCQkud2lkdGggICA9IDUsCj4gKwkJLnRhYmxlID0gbWVzb244Yl9wcmVkaXZf ZGl2X3RhYmxlLAo+ICsJCS5mbGFncyA9IENMS19ESVZJREVSX0lOVkFMSURfWkVSTywKPiArCX0s Cj4gKwkuaHcuaW5pdCA9ICYoc3RydWN0IGNsa19pbml0X2RhdGEpewo+ICsJCS5uYW1lID0gImhk bWlfcHJlZGl2IiwKPiArCQkub3BzID0gJmNsa19yZWdtYXBfZGl2aWRlcl9vcHMsCj4gKwkJLnBh cmVudF9kYXRhID0gJihjb25zdCBzdHJ1Y3QgY2xrX3BhcmVudF9kYXRhKSB7Cj4gKwkJCS5md19u YW1lID0gInh0YWwiLAo+ICsJCQkuaW5kZXggPSAtMSwKPiArCQl9LAo+ICsJCS5udW1fcGFyZW50 cyA9IDEsCj4gKwl9LAo+ICt9Owo+ICsKPiAgc3RhdGljIHN0cnVjdCBjbGtfZml4ZWRfZmFjdG9y IGhkbWlfcGxsX2Rjb19pbiA9IHsKPiAgCS5tdWx0ID0gMiwKPiAgCS5kaXYgPSAxLAo+ICAJLmh3 LmluaXQgPSAmKHN0cnVjdCBjbGtfaW5pdF9kYXRhKXsKPiAgCQkubmFtZSA9ICJoZG1pX3BsbF9k Y29faW4iLAo+ICAJCS5vcHMgPSAmY2xrX2ZpeGVkX2ZhY3Rvcl9vcHMsCj4gLQkJLnBhcmVudF9k YXRhID0gJihjb25zdCBzdHJ1Y3QgY2xrX3BhcmVudF9kYXRhKSB7Cj4gLQkJCS5md19uYW1lID0g Inh0YWwiLAo+IC0JCQkuaW5kZXggPSAtMSwKPiArCQkucGFyZW50X2h3cyA9IChjb25zdCBzdHJ1 Y3QgY2xrX2h3ICpbXSkgewo+ICsJCQkmbWVzb244Yl9oZG1pX3ByZWRpdi5odwo+ICAJCX0sCj4g IAkJLm51bV9wYXJlbnRzID0gMSwKPiAgCX0sCgpbIC4uLiBdCgo+IEBAIC0yNzksNiArMzIxLDcg QEAgc3RhdGljIHN0cnVjdCBjbGtfcmVnbWFwIG1lc29uOGJfaGRtaV9wbGxfZGNvID0gewo+ICAJ CQkmaGRtaV9wbGxfZGNvX2luLmh3Cj4gIAkJfSwKPiAgCQkubnVtX3BhcmVudHMgPSAxLAo+ICsJ CS5mbGFncyA9IENMS19TRVRfUkFURV9QQVJFTlQsCj4gIAl9LAo+ICB9OwoKW1NldmVyaXR5OiBI aWdoXQpDYW4gcmF0ZSByZXF1ZXN0cyBmcm9tIG1lc29uOGJfaGRtaV9wbGxfZGNvIHJlYWNoIG1l c29uOGJfaGRtaV9wcmVkaXYgd2l0aG91dApDTEtfU0VUX1JBVEVfUEFSRU5UIG9uIGhkbWlfcGxs X2Rjb19pbj8KCm1lc29uOGJfaGRtaV9wbGxfZGNvIGhhcyBoZG1pX3BsbF9kY29faW4gYXMgaXRz IHBhcmVudCwgYW5kIGhkbWlfcGxsX2Rjb19pbgpoYXMgbWVzb244Yl9oZG1pX3ByZWRpdiBhcyBp dHMgcGFyZW50OgoKICBtZXNvbjhiX2hkbWlfcHJlZGl2IC0+IGhkbWlfcGxsX2Rjb19pbiAtPiBt ZXNvbjhiX2hkbWlfcGxsX2RjbwoKQmVjYXVzZSBoZG1pX3BsbF9kY29faW4gZG9lcyBub3Qgc2V0 IENMS19TRVRfUkFURV9QQVJFTlQsIHdoZW4KbWVzb244Yl9oZG1pX3ByZWRpdiByZXNldHMgdG8g MCBhbmQgcmVwb3J0cyBhIDAgSHogcmF0ZSB2aWEKQ0xLX0RJVklERVJfSU5WQUxJRF9aRVJPLCBt ZXNvbl9jbGtfcGxsX2RldGVybWluZV9yYXRlKCkgY2FsbHMKY2xrX2h3X3JvdW5kX3JhdGUoKSBv biBoZG1pX3BsbF9kY29faW4sIGFuZCBjbGtfZmFjdG9yX2RldGVybWluZV9yYXRlKCkKcmV0dXJu cyAwIHdpdGhvdXQgcm91bmRpbmcgbWVzb244Yl9oZG1pX3ByZWRpdi4KClRoaXMgY2F1c2VzIG1l c29uX2Nsa19wbGxfZGV0ZXJtaW5lX3JhdGUoKSB0byByZXR1cm4gLUVJTlZBTCBhbmQgcHJldmVu dHMKY2xrX2NhbGNfbmV3X3JhdGVzKCkgZnJvbSBwcm9wYWdhdGluZyByYXRlIGNoYW5nZXMgdG8g cHJvZ3JhbQptZXNvbjhiX2hkbWlfcHJlZGl2LiBTaG91bGQgaGRtaV9wbGxfZGNvX2luIGFsc28g aGF2ZQouZmxhZ3MgPSBDTEtfU0VUX1JBVEVfUEFSRU5UPwoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVy cy9jbGsvbWVzb24vdDctcGxsLmMgYi9kcml2ZXJzL2Nsay9tZXNvbi90Ny1wbGwuYwo+IGluZGV4 IDBhNjIyZjQ1ZmEzNjguLjI4ZDU2M2ZjYjFiZDIgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9jbGsv bWVzb24vdDctcGxsLmMKPiArKysgYi9kcml2ZXJzL2Nsay9tZXNvbi90Ny1wbGwuYwoKWyAuLi4g XQoKPiBAQCAtMjkyLDYgKzM0NiwyNCBAQCBzdGF0aWMgc3RydWN0IGNsa19yZWdtYXAgdDdfaGlm aV9wbGwgPSB7Cj4gIAl9LAo+ICB9Owo+ICAKPiArc3RhdGljIHN0cnVjdCBjbGtfcmVnbWFwIHQ3 X3BjaWVfcHJlZGl2ID0gewo+ICsJLmRhdGEgPSAmKHN0cnVjdCBjbGtfcmVnbWFwX2Rpdl9kYXRh KXsKPiArCQkub2Zmc2V0ID0gUENJRVBMTF9DVFJMMCwKPiArCQkuc2hpZnQgPSAxMCwKPiArCQku d2lkdGggPSA1LAo+ICsJCS50YWJsZSA9IHQ3X3ByZWRpdl9kaXZfdGFibGUsCj4gKwkJLmZsYWdz ID0gQ0xLX0RJVklERVJfSU5WQUxJRF9aRVJPLAo+ICsJfSwKPiArCS5ody5pbml0ID0gJihzdHJ1 Y3QgY2xrX2luaXRfZGF0YSkgewo+ICsJCS5uYW1lID0gInBjaWVfcHJlZGl2IiwKPiArCQkub3Bz ID0gJmNsa19yZWdtYXBfZGl2aWRlcl9vcHMsCj4gKwkJLnBhcmVudF9kYXRhID0gJihjb25zdCBz dHJ1Y3QgY2xrX3BhcmVudF9kYXRhKSB7Cj4gKwkJCS5md19uYW1lID0gImluMCIsCj4gKwkJfSwK PiArCQkubnVtX3BhcmVudHMgPSAxLAo+ICsJfSwKPiArfTsKClsgLi4uIF0KCj4gQEAgLTM0NSwx MCArNDEyLDExIEBAIHN0YXRpYyBzdHJ1Y3QgY2xrX3JlZ21hcCB0N19wY2llX3BsbF9kY28gPSB7 Cj4gIAkuaHcuaW5pdCA9ICYoc3RydWN0IGNsa19pbml0X2RhdGEpewo+ICAJCS5uYW1lID0gInBj aWVfcGxsX2RjbyIsCj4gIAkJLm9wcyA9ICZtZXNvbl9jbGtfcGNpZV9wbGxfb3BzLAo+IC0JCS5w YXJlbnRfZGF0YSA9ICYoY29uc3Qgc3RydWN0IGNsa19wYXJlbnRfZGF0YSkgewo+IC0JCQkuZndf bmFtZSA9ICJpbjAiLAo+ICsJCS5wYXJlbnRfaHdzID0gKGNvbnN0IHN0cnVjdCBjbGtfaHcgKltd KSB7Cj4gKwkJCSZ0N19wY2llX3ByZWRpdi5odwo+ICAJCX0sCj4gIAkJLm51bV9wYXJlbnRzID0g MSwKPiArCQkuZmxhZ3MgPSBDTEtfU0VUX1JBVEVfUEFSRU5ULAo+ICAJfSwKPiAgfTsKCltTZXZl cml0eTogSGlnaF0KV2lsbCB0N19wY2llX3ByZWRpdiAoYXMgd2VsbCBhcyBnMTJhX2hkbWlfcHJl ZGl2LCBneGJiX2hkbWlfcHJlZGl2LCBhbmQKZ3hsX2hkbWlfcHJlZGl2KSByZW1haW4gc3R1Y2sg YXQgYSBjYWNoZWQgcmF0ZSBvZiAwIEh6IGlmIHRoZSBoYXJkd2FyZQpwcmUtZGl2aWRlciBmaWVs ZCBpcyAwIGF0IGNsb2NrIHJlZ2lzdHJhdGlvbiB0aW1lPwoKdDdfcGNpZV9wbGxfZGNvIHVzZXMg bWVzb25fY2xrX3BjaWVfcGxsX29wcyBhbmQgZGVmaW5lcyBuZWl0aGVyIC50YWJsZSBub3IKLnJh bmdlOyBpdCBvbmx5IHByb2dyYW1zIFBDSUVQTExfQ1RSTDAgKGluY2x1ZGluZyBOID0gMSkgaW5z aWRlCm1lc29uX2Nsa19wY2llX3BsbF9lbmFibGUoKS4gSWYgUENJRVBMTF9DVFJMMCBoYXMgTiA9 IDAgYXQgcmVnaXN0cmF0aW9uLAp0N19wY2llX3ByZWRpdiBjYWNoZXMgYSByYXRlIG9mIDAgSHog dmlhIENMS19ESVZJREVSX0lOVkFMSURfWkVSTy4gQmVjYXVzZQpjbGtfc2V0X3JhdGUoKSBjYW5u b3QgYmUgdXNlZCBvbiB0N19wY2llX3BsbF9kY28gKG1lc29uX2Nsa19nZXRfcGxsX21heF9tdWx0 aXBsaWVyKCkKcmV0dXJucyAwIHdoZW4gbmVpdGhlciAucmFuZ2Ugbm9yIC50YWJsZSBpcyBzZXQp IGFuZCB0N19wY2llX3ByZWRpdiBkb2VzIG5vdApoYXZlIENMS19HRVRfUkFURV9OT0NBQ0hFLCB0 N19wY2llX3ByZWRpdi0+cmF0ZSBpcyBuZXZlciByZWNhbGN1bGF0ZWQgYWZ0ZXIKbWVzb25fY2xr X3BjaWVfcGxsX2VuYWJsZSgpIHdyaXRlcyBQQ0lFUExMX0NUUkwwLgoKU2ltaWxhcmx5LCBpbiBk cml2ZXJzL2Nsay9tZXNvbi9nMTJhLmMgKGcxMmFfaGRtaV9wcmVkaXYpIGFuZApkcml2ZXJzL2Ns ay9tZXNvbi9neGJiLmMgKGd4YmJfaGRtaV9wcmVkaXYgYW5kIGd4bF9oZG1pX3ByZWRpdiksIHRo ZSBIRE1JIFBMTApyZWdpc3RlcnMgYXJlIHdyaXR0ZW4gZGlyZWN0bHkgYnkgdGhlIERSTSBkcml2 ZXIgaW4KZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX3ZjbGsuYyByYXRoZXIgdGhhbiB0aHJv dWdoIGNsa19zZXRfcmF0ZSgpLiBXaGlsZQpoZG1pX3BsbF9kY28gaGFzIENMS19HRVRfUkFURV9O T0NBQ0hFLCBjbGtfY29yZV9nZXRfcmF0ZV9yZWNhbGMoKSBvbmx5CnJlY2FsY3VsYXRlcyBkb3du d2FyZCBmcm9tIHRoZSBjbG9jayB3aXRoIENMS19HRVRfUkFURV9OT0NBQ0hFIHVzaW5nCmNvcmUt PnBhcmVudC0+cmF0ZS4gQmVjYXVzZSB0aGUgcGFyZW50IGhkbWlfcHJlZGl2IGNsb2NrcyBsYWNr CkNMS19HRVRfUkFURV9OT0NBQ0hFLCB0aGVpciBjYWNoZWQgcmF0ZSBzdGF5cyAwIEh6IGV2ZW4g YWZ0ZXIgdGhlIGRpc3BsYXkKZHJpdmVyIHByb2dyYW1zIE4gPSAxLCBjYXVzaW5nIG1lc29uX2Ns a19wbGxfcmVjYWxjX3JhdGUoKSBvbiBoZG1pX3BsbF9kY28gdG8KcmV0dXJuIDAgSHouCgpTaG91 bGQgcHJlLWRpdmlkZXJzIHdob3NlIHJlZ2lzdGVycyBhcmUgcHJvZ3JhbW1lZCBvdXRzaWRlIGNs a19zZXRfcmF0ZSgpIGJlCm1hcmtlZCB3aXRoIENMS19HRVRfUkFURV9OT0NBQ0hFPwoKLS0gClNh c2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2FzaGlrby5kZXYvIy9wYXRjaHNldC8yMDI2MTAy OS1tZXNvbl9yZWZhY3Rvcl9uLXYyLTAtZmY0YWM3NGU1MjdiQGFtbG9naWMuY29tP3BhcnQ9MwoK X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYW1s b2dpYyBtYWlsaW5nIGxpc3QKbGludXgtYW1sb2dpY0BsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6 Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYW1sb2dpYwo=