Re: [PATCH 6/8] drm/msm/a6xx: Add IFPC tables for Adreno 640/680

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] drm/msm/a6xx: Adreno 680 omitted from WFI config in a6xx_set_hwcg()
- [Medium] drm/msm/a6xx: perfcntr SELECT regs lost across IFPC on A6xx
--

commit bea4548efa02d7657c1bf9c8e91e5ce4b34bbd1a
Author: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

drm/msm/a6xx: Add IFPC tables for Adreno 640/680

This commit adds the powerup register list for Adreno 640 and 680 and
enables ADRENO_QUIRK_IFPC along with the IFPC and powerup register tables
in the catalog entries for both GPUs.

> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 5e1d91a73a4e1..89829fa8f4f46 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c

[ ... ]

> @@ -1115,7 +1152,8 @@ static const struct adreno_info a6xx_gpus[] = {
>  		},
>  		.gmem = SZ_1M,
>  		.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> -			  ADRENO_QUIRK_4GB_VA,
> +			  ADRENO_QUIRK_4GB_VA |
> +			  ADRENO_QUIRK_IFPC,
>  		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
>  		.funcs = &a6xx_gpu_funcs,
>  		.zapfw = "a640_zap.mdt",
> @@ -1124,6 +1162,8 @@ static const struct adreno_info a6xx_gpus[] = {
>  			.protect = &a630_protect,
>  			.gmu_cgc_mode = 0x00020202,
>  			.prim_fifo_threshold = 0x00180000,
> +			.ifpc_reglist = &a630_ifpc_reglist,
> +			.pwrup_reglist = &a640_pwrup_reglist,

[Severity: Medium]
When global performance counter streaming (MSM_PERFCNTR_STREAM) is active
via DRM_IOCTL_MSM_PERFCNTR_CONFIG, sample_worker() only inhibits IFPC while
reading the counter registers and re-enables IFPC between sampling
intervals, relying on pwrup_reglist to restore the configured SELECT
registers on IFPC exit.

However, in drivers/gpu/drm/msm/adreno/a6xx_gpu.c,
a6xx_perfcntr_configure() only populates pwrup_reglist_ptr on A7xx:

	if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) {
		WARN_ON(!a6xx_gpu->pwrup_reglist_emitted);

		struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr;
		...

With ADRENO_QUIRK_IFPC enabled on Adreno 640 and 680, won't GX power
collapse during IFPC reset the performance counter SELECT registers without
SQE restoring them when exiting IFPC?

>  		},
>  		.speedbins = ADRENO_SPEEDBINS(
>  			{ 0, 0 },
> @@ -1238,7 +1278,8 @@ static const struct adreno_info a6xx_gpus[] = {
>  		},
>  		.gmem = SZ_2M,
>  		.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> -			  ADRENO_QUIRK_4GB_VA,
> +			  ADRENO_QUIRK_4GB_VA |
> +			  ADRENO_QUIRK_IFPC,
>  		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
>  		.funcs = &a6xx_gpu_funcs,
>  		.zapfw = "a640_zap.mdt",
> @@ -1247,6 +1288,8 @@ static const struct adreno_info a6xx_gpus[] = {
>  			.protect = &a630_protect,
>  			.gmu_cgc_mode = 0x00020202,
>  			.prim_fifo_threshold = 0x00200200,
> +			.ifpc_reglist = &a630_ifpc_reglist,
> +			.pwrup_reglist = &a640_pwrup_reglist,

[Severity: Medium]
During hardware initialization (hw_init() -> a6xx_set_hwcg()),
drivers/gpu/drm/msm/adreno/a6xx_gpu.c configures
REG_A6XX_GMU_CX_GMU_WFI_CONFIG based on the GPU revision:

	/* TODO: Also A620 */
	if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
		gmu_wfi_config = 0x2;
	else
		gmu_wfi_config = 0;

	...
	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_WFI_CONFIG,
			state ? gmu_wfi_config : 0);

Because adreno_is_a640() only matches revn 640 rather than
adreno_is_a640_family() (which matches ADRENO_6XX_GEN2 for both Adreno 640
and Adreno 680), Adreno 680 will program REG_A6XX_GMU_CX_GMU_WFI_CONFIG to
0 instead of 0x2 despite sharing a640_gmu.bin, a640_hwcg, gmu_cgc_mode, and
a640_pwrup_reglist with Adreno 640.

Should a6xx_set_hwcg() check adreno_is_a640_family(adreno_gpu) so that
Adreno 680 also sets gmu_wfi_config = 0x2 with IFPC enabled?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-topic-a6xx_ifpc-v1-0-6992841a9a32@oss.qualcomm.com?part=6