From: sashiko-bot@kernel.org
To: "Leo Yan" <leo.yan@arm.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v3 05/14] perf cs-etm: Use the recorded instruction size for A32 and A64
Date: Fri, 30 Oct 2026 15:26:21 +0000 [thread overview]
Message-ID: <sashiko-outbox-191171@kernel.org> (raw)
In-Reply-To: <20261030-perf_cs_etm_fix_non_taken-v3-5-7629b52ab047@arm.com>
> Use packet->last_instr_size in cs_etm__instr_size() instead of a
> hard-coded value of four. Ordinary A32/A64 instruction ranges are
> unchanged, since their instructions are always four bytes.
>
> Prepare for synthesizing exception entries separately from the preceding
> instruction range. An exception packet may have last_instr_size = 0,
> meaning that no instruction completed at the exception source PC and the
> exception return address must not advance past that PC. The thread stack
> computes the return address as the source PC plus the instruction size,
> so returning four would incorrectly advance the return address by four
> bytes.
>
> Keep per-address decoding for T32. A range can mix 16-bit and 32-bit
> instructions, so last_instr_size describes only the final instruction
> and cannot determine the size at an arbitrary address in the range.
>
> Reviewed-by: James Clark <james.clark@linaro.org>
> Signed-off-by: Leo Yan <leo.yan@arm.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-perf_cs_etm_fix_non_taken-v3-0-7629b52ab047@arm.com?part=5
next prev parent reply other threads:[~2026-10-30 15:26 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-30 15:13 [PATCH v3 00/14] perf cs-etm: Fix bogus branch samples on exceptions Leo Yan
2026-10-30 15:13 ` [PATCH v3 01/14] perf sample: Allow decoders to supply branch return addresses Leo Yan
2026-10-30 15:20 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 02/14] perf intel-pt: Preserve return addresses for asynchronous branches Leo Yan
2026-10-30 15:25 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 03/14] perf cs-etm: Break branch history when instruction memory is unavailable Leo Yan
2026-10-30 15:24 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 04/14] perf cs-etm: Centralize packet ISA initialization Leo Yan
2026-10-30 15:17 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 05/14] perf cs-etm: Use the recorded instruction size for A32 and A64 Leo Yan
2026-10-30 15:26 ` sashiko-bot [this message]
2026-10-30 15:13 ` [PATCH v3 06/14] perf cs-etm: Mark branches that were not taken Leo Yan
2026-10-30 15:21 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 07/14] perf cs-etm: Factor out final instruction sample synthesis Leo Yan
2026-10-30 15:17 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 08/14] perf cs-etm: Centralize branch sample synthesis checks Leo Yan
2026-10-30 15:20 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 09/14] perf cs-etm: Classify exception calls using the exception packet Leo Yan
2026-10-30 15:22 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 10/14] perf cs-etm: Synthesize exception entries separately from branches Leo Yan
2026-10-30 15:40 ` sashiko-bot
2026-10-30 17:27 ` Leo Yan
2026-10-30 15:13 ` [PATCH v3 11/14] perf tests: Check CoreSight IRQ entry and exit Leo Yan
2026-10-30 15:22 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 12/14] perf tests: Check CoreSight syscall " Leo Yan
2026-10-30 15:24 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 13/14] perf tests: Check CoreSight abort " Leo Yan
2026-10-30 15:24 ` sashiko-bot
2026-10-30 15:13 ` [PATCH v3 14/14] perf tests: Check CoreSight emulated instruction " Leo Yan
2026-10-30 15:24 ` sashiko-bot
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