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From: sashiko-bot@kernel.org
To: "Gaurav Kohli" <gaurav.kohli@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v2 5/6] arm64: dts: qcom: kodiak: use thermal hw-bin trips
Date: Sat, 31 Oct 2026 13:35:37 +0000	[thread overview]
Message-ID: <sashiko-outbox-191978@kernel.org> (raw)
In-Reply-To: <20261031-thermal_bin-v2-5-d76fd073ae98@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] arm64: dts: qcom: kodiak: duplicate @180 unit-address in qfprom
--

commit 04541134a8b551c93d77860ba606f4cd37e5c12a
Author: Amit Kucheria <amit.kucheria@oss.qualcomm.com>

arm64: dts: qcom: kodiak: use thermal hw-bin trips

This commit adds jtag-id and feat-id qfprom nvmem cells to the tsens nodes
in kodiak.dtsi and updates passive thermal trip points to use per-bin
temperatures.

> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> index 347815e5983e4..b984cf47b70eb 100644
> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> @@ -1019,6 +1019,18 @@ gpu_speed_bin: gpu-speed-bin@1e9 {
>  				reg = <0x1e9 0x2>;
>  				bits = <5 8>;
>  			};
> +
> +			jtag_id: jtag-id@180 {
> +				reg = <0x180 0x4>;
> +				/* bits = <offset width>: 20 bits at offset 0 */
> +				bits = <0 20>;
> +			};
> +
> +			feat_id: feat-id@180 {
> +				reg = <0x180 0x4>;
> +				/* bits = <offset width>: 8 bits at offset 20 */
> +				bits = <20 8>;
> +			};
>  		};

[Severity: Low]
Since both jtag-id@180 and feat-id@180 are enabled sibling subnodes under
qfprom (efuse@784000) with the same @180 unit-address, won't building DTBs
with W=1 or W=2 trigger a duplicate unit-address warning from
check_unique_unit_address_common() in scripts/dtc/checks.c?

In Qualcomm QFPROM nodes (such as gpu-speed-bin@1e9 just above, which
qfprom_fixup_dt_cell_info() in drivers/nvmem/qfprom.c aligns down to a
4-byte word boundary at runtime), sub-word nvmem cells are normally
addressed by their starting byte offset with a bit offset in 0..7.

Should jtag-id@180 use reg = <0x180 0x3> with bits = <0 20>, and feat-id
be defined as feat-id@182 with reg = <0x182 0x2> and bits = <4 8>, placed
before gpu-speed-bin@1e9 in ascending unit-address order?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261031-thermal_bin-v2-0-d76fd073ae98@oss.qualcomm.com?part=5

  reply	other threads:[~2026-10-31 13:35 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-31 13:22 [PATCH v2 0/6] thermal: Add hardware-binned trip point support Gaurav Kohli
2026-10-31 13:22 ` [PATCH v2 1/6] dt-bindings: thermal: thermal-zones: add hardware-binning trip properties Gaurav Kohli
2026-10-31 13:22 ` [PATCH v2 2/6] thermal: add hardware-binning trip-point filtering support Gaurav Kohli
2026-10-31 13:40   ` sashiko-bot
2026-10-31 13:22 ` [PATCH v2 3/6] dt-bindings: thermal: qcom-tsens: document qcm6490 tsens Gaurav Kohli
2026-10-31 13:22 ` [PATCH v2 4/6] thermal: qcom: tsens: add hardware-bin trip-point filtering Gaurav Kohli
2026-10-31 13:36   ` sashiko-bot
2026-10-31 13:22 ` [PATCH v2 5/6] arm64: dts: qcom: kodiak: use thermal hw-bin trips Gaurav Kohli
2026-10-31 13:35   ` sashiko-bot [this message]
2026-10-31 13:22 ` [PATCH v2 6/6] arm64: dts: qcom: hamoa: add thermal hw-bin support Gaurav Kohli

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