Re: [PATCH 5/6] perf/x86/intel/pt: Reset stale MSR state on CPU start and resume

[sashiko-bot@kernel.org]

> The Intel PT driver caches the last values written to
> IA32_RTIT_OUTPUT_BASE, IA32_RTIT_OUTPUT_MASK_PTRS and IA32_RTIT_ADDRn_A/B,
> and skips redundant WRMSRs.  Those cached values are not invalidated when
> the hardware state changes outside the driver's control.
> 
> After S3, hibernation, CPU replacement, or similar events, the hardware
> MSRs may be reset while the cached copies retain their old values.
> Conversely, after warm reboot, kexec or kdump, the MSRs may retain values
> from a previous kernel while the cached copies start at zero.  In either
> case, the cached state no longer matches the hardware state and the
> driver can wrongly skip WRMSRs that must be issued.
> 
> In particular, after resume the driver can restart tracing with
> OUTPUT_BASE left at its reset value of 0.  Depending on the output mode,
> this may cause Intel PT to write trace data to unintended physical
> [ ... ]
> 
> Fixes: 295c52ee1485 ("perf/x86/intel/pt: Prevent redundant WRMSRs")
> Fixes: eadf48cab4b6 ("perf/x86/intel/pt: Add support for address range filtering in PT")
> Fixes: 9a6694cfa239 ("perf/x86/intel/pt: Do not force sync packets on every schedule-in")
> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261102074039.26983-1-adrian.hunter@intel.com?part=5