From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793609581; b=Z+iQ507CgDKvOOZY5+ROT7mSKErPcjd54A5YFh0GzC0ale6M9rQ5ZNLVltCVuw96qEkF Iuau1UBo2DWHm3eMW2pNBRiLHNIkzQ5nTTo6CAijMOv1aRUOadW3Mzu08U+xv3aaLZuVP tyUVpAIUH14MaL4EHeKOCmrCBBTtN9UNUZIt3cYZoq38mRXFJcIrALgx34stjG38gIKxX Q+n3D0zY+iOQth6CVolws7cPpfPhd50qB4OKNDLeCCY+8K4S3wlvS3S3PZTW5KrtE9lw9 cFunBR7X1GQHAz39EnHFLnf/Z9B/um1mAPxQacOk3TSCq3zmIB7O5DAQdwGBMR3ljjA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793609581; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=olhcOgpyJpdj24/zWw8LbBmaXBNaz23qSWupiGvbEe8=; b=KEcEYSoKksgv8oZ5LyiwL1GRPAuq/qmAk4VrwSLIFYMgA3yVduMEjMmTe5yUSKoRG6qt gLX5ErDds9vvHs6b4+BBs7n90U6VOoj6sVey+N1uv/yQ27i4dLUc3lG/3rJKf2nTI/bhH e4PXjk8oHUFBxJysuqiMM5D6Zfs9NwDJKNwgInCKmpPXprs57V7HXO8IEtWYMNgBvLcWX OK5giAU+H9fGk+DHDy10mt1/dYBxk73sAmdHfKoyvFvUr18RINlAdRt9gF9KTa9jNVUxu BGH+071pgo6RuEYXwPSFkqx1hDM5Znl1Ib1nwFoeCLFCuZ3q/WoAWrj3IbY7ueS194Q== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=Ocgb2Ngv; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC300606A324 for ; Mon, 2 Nov 2026 08:53:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=Ocgb2Ngv Received: by smtp.kernel.org (Postfix) with ESMTPSA id E872D1F000C1; Mon, 2 Nov 2026 08:52:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793609580; bh=olhcOgpyJpdj24/zWw8LbBmaXBNaz23qSWupiGvbEe8=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=Ocgb2NgvVsAzYNc+ObwrBJdeK6M3bi183ETVmMipp3Af28CFJHPrETnvBPrGnOCly QaaHA0bAcE8P/xI6w1ypFh0gGuGcdHX0gAvHTYQo2VjAFkxPt2SnmC1SLbAUyEek3S 6wAeCNMi8v3Am+imnkcVhTQ12dOd6E9vC4QmkW8lbrKbsCXWBdfftZ7Igssg10QjKg Wt8toXbdD8ltcmGebsLvdTNQ4vHRdscbMEXdI94PczoRjQNJVmZjvmNT6K+XCTQidl aOhcfqHSpQkaomNh6La2Q9SbBW+gcTTclp5Uvz+duqNWaEQQeE+3WUXDcdwXNSDb2D iP6e0VnXD3AfA== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH 3/3] arm64: dts: cix: add Sky1 USB/DP combo PHY Reply-To: sashiko-reviews@lists.linux.dev To: "Gary Yang" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261102082112.2306326-4-gary.yang@cixtech.com> References: <20261102082112.2306326-1-gary.yang@cixtech.com> <20261102082112.2306326-4-gary.yang@cixtech.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Mon, 02 Nov 2026 08:52:59 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 5 potential issue(= s) to consider: - [High] phy: cix: link rate unit mismatch and PLL disable in udphy_dp_phy_= set_rate() - [High] phy: cix: unclocked MMIO and lane check in udphy_dp_phy_configure() - [High] phy: cix: clock leak and skipped re-init in cix_usbdp_phy_power_on= () - [Medium] phy: cix: per-lane voltages ignored in udphy_dp_phy_set_voltages= () - [Medium] dt-bindings: phy: cix,sky1-usbdp-phy: missing OF graph port prop= erties -- commit ffe7df98ad72d8c1a7362fd9f434e85648138040 Author: Gary Yang arm64: dts: cix: add Sky1 USB/DP combo PHY This series adds the device tree binding, driver, and device tree nodes for the CIX Sky1 USB/DP combo PHY, supporting SuperSpeedPlus USB and DisplayPort lane muxing and Type-C orientation switching via the S5 system controller. > diff --git a/Documentation/devicetree/bindings/phy/cix,sky1-usbdp-phy.yam= l b/Documentation/devicetree/bindings/phy/cix,sky1-usbdp-phy.yaml > new file mode 100644 > index 0000000000000..a5b6943f84ebd > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/cix,sky1-usbdp-phy.yaml > @@ -0,0 +1,150 @@ [ ... ] > + orientation-switch: > + description: > + The PHY handles Type-C plug orientation switching. > + type: boolean > + > + mode-switch: > + description: > + The PHY handles multiplexing of the USB and DisplayPort lanes. > + type: boolean [Severity: Medium] When a board device tree connects a usb-c-connector node to this PHY for Type-C orientation and mode switching, the connector links to the provider via OF graph port or ports endpoints (matched by fwnode_graph_devcon_matche= s() in typec_switch_match() and typec_mux_match()). Because this schema specifies additionalProperties: false without defining port or ports properties, won't board device trees that wire a Type-C connector to a cix,sky1-usbdp-phy node fail dtbs_check validation? [ ... ] > diff --git a/drivers/phy/cix/phy-cix-usbdp.c b/drivers/phy/cix/phy-cix-us= bdp.c > new file mode 100644 > index 0000000000000..d596e89c74f76 > --- /dev/null > +++ b/drivers/phy/cix/phy-cix-usbdp.c > @@ -0,0 +1,1477 @@ [ ... ] > +static int sky1_udphy_init(struct cix_udphy *udphy) > +{ > + int ret; > + u32 value; > + const struct cix_udphy_con_dir *con_dir =3D &udphy->cfg->con_dir[udphy-= >id]; > + > + regmap_update_bits(udphy->usbphy_syscon, con_dir->offset, > + GENMASK(con_dir->bit, con_dir->bit), > + udphy->flip << con_dir->bit); > + > + usleep_range(10, 20); > + > + regmap_read(udphy->usbphy_syscon, con_dir->offset, &value); > + > + /* usb rcsu reset is default deassert */ > + reset_control_assert(udphy->reset); > + reset_control_assert(udphy->preset); > + > + ret =3D sky1_udphy_clk_enable(udphy->apb_clk); > + if (ret) { > + dev_err(udphy->dev, "Failed to prepare_enable udphy apb clock\n"); > + return ret; > + } [ ... ] > +static int udphy_orien_sw_set(struct typec_switch_dev *sw, > + enum typec_orientation orien) > +{ > + struct cix_udphy *udphy =3D typec_switch_get_drvdata(sw); > + > + mutex_lock(&udphy->mutex); > + > + if (orien =3D=3D TYPEC_ORIENTATION_NONE) > + goto unlock_ret; > + > + udphy->flip =3D (orien =3D=3D TYPEC_ORIENTATION_REVERSE) ? true : false; > + > +unlock_ret: > + mutex_unlock(&udphy->mutex); > + return 0; > +} [ ... ] > +static int cix_usbdp_phy_power_on(struct cix_udphy *udphy) > +{ > + const struct cix_udphy_cfg *phy_cfgs =3D udphy->cfg; > + int ret; > + > + if (udphy->cur_mode =3D=3D udphy->next_mode) > + return 0; > + > + if ((udphy->cur_mode =3D=3D UDPHY_MODE_USB || udphy->cur_mode =3D=3D UD= PHY_MODE_DP) && > + udphy->next_mode =3D=3D UDPHY_MODE_DP_USB) > + return 0; > + > + if (phy_cfgs->udphy_init) { > + ret =3D phy_cfgs->udphy_init(udphy); > + if (ret) { > + dev_err(udphy->dev, "failed to init udphy\n"); > + return ret; > + } > + } > + > + return 0; > +} [ ... ] > +static int udphy_dp_phy_power_on(struct phy *phy) > +{ > + struct cix_udphy *udphy =3D phy_get_drvdata(phy); > + int ret =3D 0; > + > + mutex_lock(&udphy->mutex); > + if (!(udphy->next_mode & UDPHY_MODE_DP)) > + goto unlock; > + > + ret =3D cix_usbdp_phy_power_on(udphy); > + if (ret) > + goto unlock; > + > + phy_set_bus_width(phy, udphy_dplane_get(udphy)); > + if (udphy->next_mode =3D=3D UDPHY_MODE_DP) > + udphy->cur_mode =3D UDPHY_MODE_DP; > + else > + udphy->cur_mode |=3D UDPHY_MODE_DP; > + > +unlock: > + mutex_unlock(&udphy->mutex); > + return ret; > +} [Severity: High] How are udphy->apb_clk and the hardware lane configuration kept in sync when transitioning between Type-C modes and orientations? First, if USB powers on first (setting udphy->cur_mode =3D UDPHY_MODE_USB a= nd enabling udphy->apb_clk once in sky1_udphy_init()), and the Type-C mux then selects 4-lane DP (udphy->next_mode =3D UDPHY_MODE_DP) followed by udphy_dp_phy_power_on(): udphy_dp_phy_power_on() cix_usbdp_phy_power_on() sky1_udphy_init() sky1_udphy_clk_enable(udphy->apb_clk); udphy->cur_mode =3D UDPHY_MODE_DP; sky1_udphy_init() calls clk_prepare_enable(udphy->apb_clk) a second time, a= nd udphy_dp_phy_power_on() overwrites udphy->cur_mode =3D UDPHY_MODE_DP, dropp= ing UDPHY_MODE_USB. When the PHYs later power off, sky1_udphy_exit() runs at mo= st once, leaking a prepare/enable reference on udphy->apb_clk. Second, if DP powers on first in 4-lane mode (udphy->cur_mode =3D UDPHY_MOD= E_DP, programmed with sky1_udphy_dp_conf) and udphy->next_mode later changes to UDPHY_MODE_DP_USB, cix_usbdp_phy_power_on() hits the early return: if ((udphy->cur_mode =3D=3D UDPHY_MODE_USB || udphy->cur_mode =3D=3D UDPHY= _MODE_DP) && udphy->next_mode =3D=3D UDPHY_MODE_DP_USB) return 0; Doesn't that skip reprogramming the PHY from 4-lane DP to the USB+DP combo configuration when cix_u3phy_init() is called? Third, if udphy_orien_sw_set() updates udphy->flip while one sub-PHY is already active in udphy->cur_mode, cix_usbdp_phy_power_on() also returns 0 without updating udphy->usbphy_syscon or loading the flipped register table (sky1_udphy_usbdp_conf_flip), while subsequent calls to udphy_dp_phy_set_rate() and udphy_dp_phy_set_voltages() program the flipped lanes. [ ... ] > +static int udphy_dp_phy_verify_config(struct cix_udphy *udphy, > + struct phy_configure_opts_dp *dp) > +{ > + int i; > + > + switch (dp->lanes) { > + case 1: > + case 2: > + case 4: > + break; > + default: > + return -EINVAL; > + } [ ... ] > +static int udphy_dp_phy_set_rate(struct cix_udphy *udphy, > + struct phy_configure_opts_dp *dp) > +{ > + int ret; > + const struct phy_link_cfg *conf =3D NULL; > + > + dev_dbg(udphy->dev, "lane %d, rate %x\n", dp->lanes, dp->link_rate); > + > + regmap_update_bits(udphy->phy_regmap, PHY_PMA_PLL_CTRL, BIT(1), 0x0); > + usleep_range(10, 20); > + > + switch (dp->link_rate) { > + case 0x6: > + conf =3D &link_cfg[0]; > + ret =3D regmap_multi_reg_write(udphy->phy_regmap, sky1_udphy_dp_partia= l_conf, > + ARRAY_SIZE(sky1_udphy_dp_partial_conf)); > + break; > + case 0xa: > + conf =3D &link_cfg[1]; > + ret =3D regmap_multi_reg_write(udphy->phy_regmap, sky1_udphy_dp_partia= l_conf, > + ARRAY_SIZE(sky1_udphy_dp_partial_conf)); > + break; > + case 0x14: > + conf =3D &link_cfg[2]; > + ret =3D regmap_multi_reg_write(udphy->phy_regmap, sky1_udphy_dp_partia= l_conf, > + ARRAY_SIZE(sky1_udphy_dp_partial_conf)); > + break; > + case 0x1e: > + conf =3D &link_cfg[3]; > + ret =3D regmap_multi_reg_write(udphy->phy_regmap, sky1_udphy_dp_8p1_co= nf, > + ARRAY_SIZE(sky1_udphy_dp_8p1_conf)); > + break; > + default: > + return -EINVAL; > + } [Severity: High] In include/linux/phy/phy-dp.h, struct phy_configure_opts_dp defines link_ra= te in Mb/s (1620, 2700, 5400, 8100), whereas udphy_dp_phy_set_rate() matches dp->link_rate against raw DPCD bandwidth codes (0x6, 0xa, 0x14, 0x1e). Won't standard DisplayPort controller drivers passing link_rate in Mb/s to phy_configure() -> udphy_dp_phy_configure() -> udphy_dp_phy_set_rate() alwa= ys hit the default case and fail with -EINVAL, while also leaving BIT(1) of PHY_PMA_PLL_CTRL cleared? [ ... ] > +static int udphy_dp_phy_set_voltages(struct cix_udphy *udphy, > + struct phy_configure_opts_dp *dp) > +{ > + u32 index =3D dp->voltage[0] * 4 + dp->pre[0]; > + const struct phy_voltage_conf *cfg =3D volt_cfg; > + > + dev_dbg(udphy->dev, "lane %d, vs %d, pe %d\n", dp->lanes, dp->voltage[0= ], > + dp->pre[0]); [Severity: Medium] udphy_dp_phy_verify_config() validates dp->voltage[i] and dp->pre[i] for ea= ch lane i < dp->lanes, but udphy_dp_phy_set_voltages() computes index solely f= rom dp->voltage[0] and dp->pre[0] and writes that configuration to all active lanes. Should udphy_dp_phy_set_voltages() compute the volt_cfg index per lane using each lane's own dp->voltage[i] and dp->pre[i] values so per-lane link train= ing adjustments are applied? [ ... ] > +static int udphy_dp_phy_configure(struct phy *phy, > + union phy_configure_opts *opts) > +{ > + struct cix_udphy *udphy =3D phy_get_drvdata(phy); > + int ret; > + > + mutex_lock(&udphy->mutex); > + ret =3D udphy_dp_phy_verify_config(udphy, &opts->dp); > + if (ret) > + goto unlock; > + > + if (opts->dp.set_rate) { > + ret =3D udphy_dp_phy_set_rate(udphy, &opts->dp); > + if (ret) { > + dev_err(udphy->dev, "failed to set DP link rate\n"); > + goto unlock; > + } > + } [Severity: High] What happens if udphy_dp_phy_configure() is called when UDPHY_MODE_DP is not active in udphy->cur_mode, or with more lanes than allocated to DP? In udphy_dp_phy_power_on(), if !(udphy->next_mode & UDPHY_MODE_DP) (for example when Type-C is in TYPEC_STATE_SAFE or USB-only mode, or when cix,default-conf is 0 or 1), udphy_dp_phy_power_on() returns 0 without enabling udphy->apb_clk or deasserting udphy->preset. A subsequent call to udphy_dp_phy_configure() will then perform MMIO reads and writes through udphy->phy_regmap while the APB clock is disabled and APB reset is asserted. In addition, udphy_dp_phy_verify_config() accepts dp->lanes =3D=3D 4 without checking against udphy_dplane_get(udphy), so a 4-lane DP configuration in 2-lane UDPHY_MODE_DP_USB mode will overwrite the active USB lane registers = in udphy_dp_phy_set_rate() and udphy_dp_phy_set_voltages(). --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261102082112.2306= 326-1-gary.yang@cixtech.com?part=3D3 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C8BC606A32C for ; Mon, 2 Nov 2026 08:53:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 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b=Ocgb2NgvVsAzYNc+ObwrBJdeK6M3bi183ETVmMipp3Af28CFJHPrETnvBPrGnOCly QaaHA0bAcE8P/xI6w1ypFh0gGuGcdHX0gAvHTYQo2VjAFkxPt2SnmC1SLbAUyEek3S 6wAeCNMi8v3Am+imnkcVhTQ12dOd6E9vC4QmkW8lbrKbsCXWBdfftZ7Igssg10QjKg Wt8toXbdD8ltcmGebsLvdTNQ4vHRdscbMEXdI94PczoRjQNJVmZjvmNT6K+XCTQidl aOhcfqHSpQkaomNh6La2Q9SbBW+gcTTclp5Uvz+duqNWaEQQeE+3WUXDcdwXNSDb2D iP6e0VnXD3AfA== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH 3/3] arm64: dts: cix: add Sky1 USB/DP combo PHY To: "Gary Yang" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261102082112.2306326-4-gary.yang@cixtech.com> References: <20261102082112.2306326-1-gary.yang@cixtech.com> <20261102082112.2306326-4-gary.yang@cixtech.com> Date: Mon, 02 Nov 2026 08:52:59 +0000 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg NSBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIHBoeTogY2l4OiBsaW5r IHJhdGUgdW5pdCBtaXNtYXRjaCBhbmQgUExMIGRpc2FibGUgaW4gdWRwaHlfZHBfcGh5X3NldF9y YXRlKCkKLSBbSGlnaF0gcGh5OiBjaXg6IHVuY2xvY2tlZCBNTUlPIGFuZCBsYW5lIGNoZWNrIGlu IHVkcGh5X2RwX3BoeV9jb25maWd1cmUoKQotIFtIaWdoXSBwaHk6IGNpeDogY2xvY2sgbGVhayBh bmQgc2tpcHBlZCByZS1pbml0IGluIGNpeF91c2JkcF9waHlfcG93ZXJfb24oKQotIFtNZWRpdW1d IHBoeTogY2l4OiBwZXItbGFuZSB2b2x0YWdlcyBpZ25vcmVkIGluIHVkcGh5X2RwX3BoeV9zZXRf dm9sdGFnZXMoKQotIFtNZWRpdW1dIGR0LWJpbmRpbmdzOiBwaHk6IGNpeCxza3kxLXVzYmRwLXBo eTogbWlzc2luZyBPRiBncmFwaCBwb3J0IHByb3BlcnRpZXMKLS0KCmNvbW1pdCBmZmU3ZGY5OGFk NzJkOGMxYTczNjJmZDlmNDM0ZTg1NjQ4MTM4MDQwCkF1dGhvcjogR2FyeSBZYW5nIDxnYXJ5Lnlh bmdAY2l4dGVjaC5jb20+Cgphcm02NDogZHRzOiBjaXg6IGFkZCBTa3kxIFVTQi9EUCBjb21ibyBQ SFkKClRoaXMgc2VyaWVzIGFkZHMgdGhlIGRldmljZSB0cmVlIGJpbmRpbmcsIGRyaXZlciwgYW5k IGRldmljZSB0cmVlIG5vZGVzIGZvcgp0aGUgQ0lYIFNreTEgVVNCL0RQIGNvbWJvIFBIWSwgc3Vw cG9ydGluZyBTdXBlclNwZWVkUGx1cyBVU0IgYW5kIERpc3BsYXlQb3J0CmxhbmUgbXV4aW5nIGFu ZCBUeXBlLUMgb3JpZW50YXRpb24gc3dpdGNoaW5nIHZpYSB0aGUgUzUgc3lzdGVtIGNvbnRyb2xs ZXIuCgo+IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGh5 L2NpeCxza3kxLXVzYmRwLXBoeS55YW1sIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL3BoeS9jaXgsc2t5MS11c2JkcC1waHkueWFtbAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4g aW5kZXggMDAwMDAwMDAwMDAwMC4uYTViNjk0M2Y4NGViZAo+IC0tLSAvZGV2L251bGwKPiArKysg Yi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGh5L2NpeCxza3kxLXVzYmRwLXBo eS55YW1sCj4gQEAgLTAsMCArMSwxNTAgQEAKClsgLi4uIF0KCj4gKyAgb3JpZW50YXRpb24tc3dp dGNoOgo+ICsgICAgZGVzY3JpcHRpb246Cj4gKyAgICAgIFRoZSBQSFkgaGFuZGxlcyBUeXBlLUMg cGx1ZyBvcmllbnRhdGlvbiBzd2l0Y2hpbmcuCj4gKyAgICB0eXBlOiBib29sZWFuCj4gKwo+ICsg IG1vZGUtc3dpdGNoOgo+ICsgICAgZGVzY3JpcHRpb246Cj4gKyAgICAgIFRoZSBQSFkgaGFuZGxl cyBtdWx0aXBsZXhpbmcgb2YgdGhlIFVTQiBhbmQgRGlzcGxheVBvcnQgbGFuZXMuCj4gKyAgICB0 eXBlOiBib29sZWFuCgpbU2V2ZXJpdHk6IE1lZGl1bV0KV2hlbiBhIGJvYXJkIGRldmljZSB0cmVl IGNvbm5lY3RzIGEgdXNiLWMtY29ubmVjdG9yIG5vZGUgdG8gdGhpcyBQSFkgZm9yClR5cGUtQyBv cmllbnRhdGlvbiBhbmQgbW9kZSBzd2l0Y2hpbmcsIHRoZSBjb25uZWN0b3IgbGlua3MgdG8gdGhl IHByb3ZpZGVyCnZpYSBPRiBncmFwaCBwb3J0IG9yIHBvcnRzIGVuZHBvaW50cyAobWF0Y2hlZCBi eSBmd25vZGVfZ3JhcGhfZGV2Y29uX21hdGNoZXMoKQppbiB0eXBlY19zd2l0Y2hfbWF0Y2goKSBh bmQgdHlwZWNfbXV4X21hdGNoKCkpLgoKQmVjYXVzZSB0aGlzIHNjaGVtYSBzcGVjaWZpZXMgYWRk aXRpb25hbFByb3BlcnRpZXM6IGZhbHNlIHdpdGhvdXQgZGVmaW5pbmcKcG9ydCBvciBwb3J0cyBw cm9wZXJ0aWVzLCB3b24ndCBib2FyZCBkZXZpY2UgdHJlZXMgdGhhdCB3aXJlIGEgVHlwZS1DCmNv bm5lY3RvciB0byBhIGNpeCxza3kxLXVzYmRwLXBoeSBub2RlIGZhaWwgZHRic19jaGVjayB2YWxp ZGF0aW9uPwoKWyAuLi4gXQoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9waHkvY2l4L3BoeS1jaXgt dXNiZHAuYyBiL2RyaXZlcnMvcGh5L2NpeC9waHktY2l4LXVzYmRwLmMKPiBuZXcgZmlsZSBtb2Rl IDEwMDY0NAo+IGluZGV4IDAwMDAwMDAwMDAwMDAuLmQ1OTZlODljNzRmNzYKPiAtLS0gL2Rldi9u dWxsCj4gKysrIGIvZHJpdmVycy9waHkvY2l4L3BoeS1jaXgtdXNiZHAuYwo+IEBAIC0wLDAgKzEs MTQ3NyBAQAoKWyAuLi4gXQoKPiArc3RhdGljIGludCBza3kxX3VkcGh5X2luaXQoc3RydWN0IGNp eF91ZHBoeSAqdWRwaHkpCj4gK3sKPiArCWludCByZXQ7Cj4gKwl1MzIgdmFsdWU7Cj4gKwljb25z dCBzdHJ1Y3QgY2l4X3VkcGh5X2Nvbl9kaXIgKmNvbl9kaXIgPSAmdWRwaHktPmNmZy0+Y29uX2Rp clt1ZHBoeS0+aWRdOwo+ICsKPiArCXJlZ21hcF91cGRhdGVfYml0cyh1ZHBoeS0+dXNicGh5X3N5 c2NvbiwgY29uX2Rpci0+b2Zmc2V0LAo+ICsJCQkgICBHRU5NQVNLKGNvbl9kaXItPmJpdCwgY29u X2Rpci0+Yml0KSwKPiArCQkJICAgdWRwaHktPmZsaXAgPDwgY29uX2Rpci0+Yml0KTsKPiArCj4g Kwl1c2xlZXBfcmFuZ2UoMTAsIDIwKTsKPiArCj4gKwlyZWdtYXBfcmVhZCh1ZHBoeS0+dXNicGh5 X3N5c2NvbiwgY29uX2Rpci0+b2Zmc2V0LCAmdmFsdWUpOwo+ICsKPiArCS8qIHVzYiByY3N1IHJl c2V0IGlzIGRlZmF1bHQgZGVhc3NlcnQgKi8KPiArCXJlc2V0X2NvbnRyb2xfYXNzZXJ0KHVkcGh5 LT5yZXNldCk7Cj4gKwlyZXNldF9jb250cm9sX2Fzc2VydCh1ZHBoeS0+cHJlc2V0KTsKPiArCj4g KwlyZXQgPSBza3kxX3VkcGh5X2Nsa19lbmFibGUodWRwaHktPmFwYl9jbGspOwo+ICsJaWYgKHJl dCkgewo+ICsJCWRldl9lcnIodWRwaHktPmRldiwgIkZhaWxlZCB0byBwcmVwYXJlX2VuYWJsZSB1 ZHBoeSBhcGIgY2xvY2tcbiIpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9CgpbIC4uLiBdCgo+ICtz dGF0aWMgaW50IHVkcGh5X29yaWVuX3N3X3NldChzdHJ1Y3QgdHlwZWNfc3dpdGNoX2RldiAqc3cs Cj4gKwkJCSAgICAgIGVudW0gdHlwZWNfb3JpZW50YXRpb24gb3JpZW4pCj4gK3sKPiArCXN0cnVj dCBjaXhfdWRwaHkgKnVkcGh5ID0gdHlwZWNfc3dpdGNoX2dldF9kcnZkYXRhKHN3KTsKPiArCj4g KwltdXRleF9sb2NrKCZ1ZHBoeS0+bXV0ZXgpOwo+ICsKPiArCWlmIChvcmllbiA9PSBUWVBFQ19P UklFTlRBVElPTl9OT05FKQo+ICsJCWdvdG8gdW5sb2NrX3JldDsKPiArCj4gKwl1ZHBoeS0+Zmxp cCA9IChvcmllbiA9PSBUWVBFQ19PUklFTlRBVElPTl9SRVZFUlNFKSA/IHRydWUgOiBmYWxzZTsK PiArCj4gK3VubG9ja19yZXQ6Cj4gKwltdXRleF91bmxvY2soJnVkcGh5LT5tdXRleCk7Cj4gKwly ZXR1cm4gMDsKPiArfQoKWyAuLi4gXQoKPiArc3RhdGljIGludCBjaXhfdXNiZHBfcGh5X3Bvd2Vy X29uKHN0cnVjdCBjaXhfdWRwaHkgKnVkcGh5KQo+ICt7Cj4gKwljb25zdCBzdHJ1Y3QgY2l4X3Vk cGh5X2NmZyAqcGh5X2NmZ3MgPSB1ZHBoeS0+Y2ZnOwo+ICsJaW50IHJldDsKPiArCj4gKwlpZiAo dWRwaHktPmN1cl9tb2RlID09IHVkcGh5LT5uZXh0X21vZGUpCj4gKwkJcmV0dXJuIDA7Cj4gKwo+ ICsJaWYgKCh1ZHBoeS0+Y3VyX21vZGUgPT0gVURQSFlfTU9ERV9VU0IgfHwgdWRwaHktPmN1cl9t b2RlID09IFVEUEhZX01PREVfRFApICYmCj4gKwkgICAgdWRwaHktPm5leHRfbW9kZSA9PSBVRFBI WV9NT0RFX0RQX1VTQikKPiArCQlyZXR1cm4gMDsKPiArCj4gKwlpZiAocGh5X2NmZ3MtPnVkcGh5 X2luaXQpIHsKPiArCQlyZXQgPSBwaHlfY2Zncy0+dWRwaHlfaW5pdCh1ZHBoeSk7Cj4gKwkJaWYg KHJldCkgewo+ICsJCQlkZXZfZXJyKHVkcGh5LT5kZXYsICJmYWlsZWQgdG8gaW5pdCB1ZHBoeVxu Iik7Cj4gKwkJCXJldHVybiByZXQ7Cj4gKwkJfQo+ICsJfQo+ICsKPiArCXJldHVybiAwOwo+ICt9 CgpbIC4uLiBdCgo+ICtzdGF0aWMgaW50IHVkcGh5X2RwX3BoeV9wb3dlcl9vbihzdHJ1Y3QgcGh5 ICpwaHkpCj4gK3sKPiArCXN0cnVjdCBjaXhfdWRwaHkgKnVkcGh5ID0gcGh5X2dldF9kcnZkYXRh KHBoeSk7Cj4gKwlpbnQgcmV0ID0gMDsKPiArCj4gKwltdXRleF9sb2NrKCZ1ZHBoeS0+bXV0ZXgp Owo+ICsJaWYgKCEodWRwaHktPm5leHRfbW9kZSAmIFVEUEhZX01PREVfRFApKQo+ICsJCWdvdG8g dW5sb2NrOwo+ICsKPiArCXJldCA9IGNpeF91c2JkcF9waHlfcG93ZXJfb24odWRwaHkpOwo+ICsJ aWYgKHJldCkKPiArCQlnb3RvIHVubG9jazsKPiArCj4gKwlwaHlfc2V0X2J1c193aWR0aChwaHks IHVkcGh5X2RwbGFuZV9nZXQodWRwaHkpKTsKPiArCWlmICh1ZHBoeS0+bmV4dF9tb2RlID09IFVE UEhZX01PREVfRFApCj4gKwkJdWRwaHktPmN1cl9tb2RlID0gVURQSFlfTU9ERV9EUDsKPiArCWVs c2UKPiArCQl1ZHBoeS0+Y3VyX21vZGUgfD0gVURQSFlfTU9ERV9EUDsKPiArCj4gK3VubG9jazoK PiArCW11dGV4X3VubG9jaygmdWRwaHktPm11dGV4KTsKPiArCXJldHVybiByZXQ7Cj4gK30KCltT ZXZlcml0eTogSGlnaF0KSG93IGFyZSB1ZHBoeS0+YXBiX2NsayBhbmQgdGhlIGhhcmR3YXJlIGxh bmUgY29uZmlndXJhdGlvbiBrZXB0IGluIHN5bmMgd2hlbgp0cmFuc2l0aW9uaW5nIGJldHdlZW4g VHlwZS1DIG1vZGVzIGFuZCBvcmllbnRhdGlvbnM/CgpGaXJzdCwgaWYgVVNCIHBvd2VycyBvbiBm aXJzdCAoc2V0dGluZyB1ZHBoeS0+Y3VyX21vZGUgPSBVRFBIWV9NT0RFX1VTQiBhbmQKZW5hYmxp bmcgdWRwaHktPmFwYl9jbGsgb25jZSBpbiBza3kxX3VkcGh5X2luaXQoKSksIGFuZCB0aGUgVHlw ZS1DIG11eCB0aGVuCnNlbGVjdHMgNC1sYW5lIERQICh1ZHBoeS0+bmV4dF9tb2RlID0gVURQSFlf TU9ERV9EUCkgZm9sbG93ZWQgYnkKdWRwaHlfZHBfcGh5X3Bvd2VyX29uKCk6CgogIHVkcGh5X2Rw X3BoeV9wb3dlcl9vbigpCiAgICBjaXhfdXNiZHBfcGh5X3Bvd2VyX29uKCkKICAgICAgc2t5MV91 ZHBoeV9pbml0KCkKICAgICAgICBza3kxX3VkcGh5X2Nsa19lbmFibGUodWRwaHktPmFwYl9jbGsp OwogICAgdWRwaHktPmN1cl9tb2RlID0gVURQSFlfTU9ERV9EUDsKCnNreTFfdWRwaHlfaW5pdCgp IGNhbGxzIGNsa19wcmVwYXJlX2VuYWJsZSh1ZHBoeS0+YXBiX2NsaykgYSBzZWNvbmQgdGltZSwg YW5kCnVkcGh5X2RwX3BoeV9wb3dlcl9vbigpIG92ZXJ3cml0ZXMgdWRwaHktPmN1cl9tb2RlID0g VURQSFlfTU9ERV9EUCwgZHJvcHBpbmcKVURQSFlfTU9ERV9VU0IuIFdoZW4gdGhlIFBIWXMgbGF0 ZXIgcG93ZXIgb2ZmLCBza3kxX3VkcGh5X2V4aXQoKSBydW5zIGF0IG1vc3QKb25jZSwgbGVha2lu ZyBhIHByZXBhcmUvZW5hYmxlIHJlZmVyZW5jZSBvbiB1ZHBoeS0+YXBiX2Nsay4KClNlY29uZCwg aWYgRFAgcG93ZXJzIG9uIGZpcnN0IGluIDQtbGFuZSBtb2RlICh1ZHBoeS0+Y3VyX21vZGUgPSBV RFBIWV9NT0RFX0RQLApwcm9ncmFtbWVkIHdpdGggc2t5MV91ZHBoeV9kcF9jb25mKSBhbmQgdWRw aHktPm5leHRfbW9kZSBsYXRlciBjaGFuZ2VzIHRvClVEUEhZX01PREVfRFBfVVNCLCBjaXhfdXNi ZHBfcGh5X3Bvd2VyX29uKCkgaGl0cyB0aGUgZWFybHkgcmV0dXJuOgoKCWlmICgodWRwaHktPmN1 cl9tb2RlID09IFVEUEhZX01PREVfVVNCIHx8IHVkcGh5LT5jdXJfbW9kZSA9PSBVRFBIWV9NT0RF X0RQKSAmJgoJICAgIHVkcGh5LT5uZXh0X21vZGUgPT0gVURQSFlfTU9ERV9EUF9VU0IpCgkJcmV0 dXJuIDA7CgpEb2Vzbid0IHRoYXQgc2tpcCByZXByb2dyYW1taW5nIHRoZSBQSFkgZnJvbSA0LWxh bmUgRFAgdG8gdGhlIFVTQitEUCBjb21ibwpjb25maWd1cmF0aW9uIHdoZW4gY2l4X3UzcGh5X2lu aXQoKSBpcyBjYWxsZWQ/CgpUaGlyZCwgaWYgdWRwaHlfb3JpZW5fc3dfc2V0KCkgdXBkYXRlcyB1 ZHBoeS0+ZmxpcCB3aGlsZSBvbmUgc3ViLVBIWSBpcwphbHJlYWR5IGFjdGl2ZSBpbiB1ZHBoeS0+ Y3VyX21vZGUsIGNpeF91c2JkcF9waHlfcG93ZXJfb24oKSBhbHNvIHJldHVybnMgMAp3aXRob3V0 IHVwZGF0aW5nIHVkcGh5LT51c2JwaHlfc3lzY29uIG9yIGxvYWRpbmcgdGhlIGZsaXBwZWQgcmVn aXN0ZXIgdGFibGUKKHNreTFfdWRwaHlfdXNiZHBfY29uZl9mbGlwKSwgd2hpbGUgc3Vic2VxdWVu dCBjYWxscyB0bwp1ZHBoeV9kcF9waHlfc2V0X3JhdGUoKSBhbmQgdWRwaHlfZHBfcGh5X3NldF92 b2x0YWdlcygpIHByb2dyYW0gdGhlIGZsaXBwZWQKbGFuZXMuCgpbIC4uLiBdCgo+ICtzdGF0aWMg aW50IHVkcGh5X2RwX3BoeV92ZXJpZnlfY29uZmlnKHN0cnVjdCBjaXhfdWRwaHkgKnVkcGh5LAo+ ICsJCQkJICAgICAgc3RydWN0IHBoeV9jb25maWd1cmVfb3B0c19kcCAqZHApCj4gK3sKPiArCWlu dCBpOwo+ICsKPiArCXN3aXRjaCAoZHAtPmxhbmVzKSB7Cj4gKwljYXNlIDE6Cj4gKwljYXNlIDI6 Cj4gKwljYXNlIDQ6Cj4gKwkJYnJlYWs7Cj4gKwlkZWZhdWx0Ogo+ICsJCXJldHVybiAtRUlOVkFM Owo+ICsJfQoKWyAuLi4gXQoKPiArc3RhdGljIGludCB1ZHBoeV9kcF9waHlfc2V0X3JhdGUoc3Ry dWN0IGNpeF91ZHBoeSAqdWRwaHksCj4gKwkJCQkgc3RydWN0IHBoeV9jb25maWd1cmVfb3B0c19k cCAqZHApCj4gK3sKPiArCWludCByZXQ7Cj4gKwljb25zdCBzdHJ1Y3QgcGh5X2xpbmtfY2ZnICpj b25mID0gTlVMTDsKPiArCj4gKwlkZXZfZGJnKHVkcGh5LT5kZXYsICJsYW5lICVkLCByYXRlICV4 XG4iLCBkcC0+bGFuZXMsIGRwLT5saW5rX3JhdGUpOwo+ICsKPiArCXJlZ21hcF91cGRhdGVfYml0 cyh1ZHBoeS0+cGh5X3JlZ21hcCwgUEhZX1BNQV9QTExfQ1RSTCwgQklUKDEpLCAweDApOwo+ICsJ dXNsZWVwX3JhbmdlKDEwLCAyMCk7Cj4gKwo+ICsJc3dpdGNoIChkcC0+bGlua19yYXRlKSB7Cj4g KwljYXNlIDB4NjoKPiArCQljb25mID0gJmxpbmtfY2ZnWzBdOwo+ICsJCXJldCA9IHJlZ21hcF9t dWx0aV9yZWdfd3JpdGUodWRwaHktPnBoeV9yZWdtYXAsIHNreTFfdWRwaHlfZHBfcGFydGlhbF9j b25mLAo+ICsJCQkJCSAgICAgQVJSQVlfU0laRShza3kxX3VkcGh5X2RwX3BhcnRpYWxfY29uZikp Owo+ICsJCWJyZWFrOwo+ICsJY2FzZSAweGE6Cj4gKwkJY29uZiA9ICZsaW5rX2NmZ1sxXTsKPiAr CQlyZXQgPSByZWdtYXBfbXVsdGlfcmVnX3dyaXRlKHVkcGh5LT5waHlfcmVnbWFwLCBza3kxX3Vk cGh5X2RwX3BhcnRpYWxfY29uZiwKPiArCQkJCQkgICAgIEFSUkFZX1NJWkUoc2t5MV91ZHBoeV9k cF9wYXJ0aWFsX2NvbmYpKTsKPiArCQlicmVhazsKPiArCWNhc2UgMHgxNDoKPiArCQljb25mID0g JmxpbmtfY2ZnWzJdOwo+ICsJCXJldCA9IHJlZ21hcF9tdWx0aV9yZWdfd3JpdGUodWRwaHktPnBo eV9yZWdtYXAsIHNreTFfdWRwaHlfZHBfcGFydGlhbF9jb25mLAo+ICsJCQkJCSAgICAgQVJSQVlf U0laRShza3kxX3VkcGh5X2RwX3BhcnRpYWxfY29uZikpOwo+ICsJCWJyZWFrOwo+ICsJY2FzZSAw eDFlOgo+ICsJCWNvbmYgPSAmbGlua19jZmdbM107Cj4gKwkJcmV0ID0gcmVnbWFwX211bHRpX3Jl Z193cml0ZSh1ZHBoeS0+cGh5X3JlZ21hcCwgc2t5MV91ZHBoeV9kcF84cDFfY29uZiwKPiArCQkJ CQkgICAgIEFSUkFZX1NJWkUoc2t5MV91ZHBoeV9kcF84cDFfY29uZikpOwo+ICsJCWJyZWFrOwo+ ICsJZGVmYXVsdDoKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCX0KCltTZXZlcml0eTogSGlnaF0K SW4gaW5jbHVkZS9saW51eC9waHkvcGh5LWRwLmgsIHN0cnVjdCBwaHlfY29uZmlndXJlX29wdHNf ZHAgZGVmaW5lcyBsaW5rX3JhdGUKaW4gTWIvcyAoMTYyMCwgMjcwMCwgNTQwMCwgODEwMCksIHdo ZXJlYXMgdWRwaHlfZHBfcGh5X3NldF9yYXRlKCkgbWF0Y2hlcwpkcC0+bGlua19yYXRlIGFnYWlu c3QgcmF3IERQQ0QgYmFuZHdpZHRoIGNvZGVzICgweDYsIDB4YSwgMHgxNCwgMHgxZSkuCgpXb24n dCBzdGFuZGFyZCBEaXNwbGF5UG9ydCBjb250cm9sbGVyIGRyaXZlcnMgcGFzc2luZyBsaW5rX3Jh dGUgaW4gTWIvcyB0bwpwaHlfY29uZmlndXJlKCkgLT4gdWRwaHlfZHBfcGh5X2NvbmZpZ3VyZSgp IC0+IHVkcGh5X2RwX3BoeV9zZXRfcmF0ZSgpIGFsd2F5cwpoaXQgdGhlIGRlZmF1bHQgY2FzZSBh bmQgZmFpbCB3aXRoIC1FSU5WQUwsIHdoaWxlIGFsc28gbGVhdmluZyBCSVQoMSkgb2YKUEhZX1BN QV9QTExfQ1RSTCBjbGVhcmVkPwoKWyAuLi4gXQoKPiArc3RhdGljIGludCB1ZHBoeV9kcF9waHlf c2V0X3ZvbHRhZ2VzKHN0cnVjdCBjaXhfdWRwaHkgKnVkcGh5LAo+ICsJCQkJICAgICBzdHJ1Y3Qg cGh5X2NvbmZpZ3VyZV9vcHRzX2RwICpkcCkKPiArewo+ICsJdTMyIGluZGV4ID0gZHAtPnZvbHRh Z2VbMF0gKiA0ICsgZHAtPnByZVswXTsKPiArCWNvbnN0IHN0cnVjdCBwaHlfdm9sdGFnZV9jb25m ICpjZmcgPSB2b2x0X2NmZzsKPiArCj4gKwlkZXZfZGJnKHVkcGh5LT5kZXYsICJsYW5lICVkLCB2 cyAlZCwgcGUgJWRcbiIsIGRwLT5sYW5lcywgZHAtPnZvbHRhZ2VbMF0sCj4gKwkJZHAtPnByZVsw XSk7CgpbU2V2ZXJpdHk6IE1lZGl1bV0KdWRwaHlfZHBfcGh5X3ZlcmlmeV9jb25maWcoKSB2YWxp ZGF0ZXMgZHAtPnZvbHRhZ2VbaV0gYW5kIGRwLT5wcmVbaV0gZm9yIGVhY2gKbGFuZSBpIDwgZHAt PmxhbmVzLCBidXQgdWRwaHlfZHBfcGh5X3NldF92b2x0YWdlcygpIGNvbXB1dGVzIGluZGV4IHNv bGVseSBmcm9tCmRwLT52b2x0YWdlWzBdIGFuZCBkcC0+cHJlWzBdIGFuZCB3cml0ZXMgdGhhdCBj b25maWd1cmF0aW9uIHRvIGFsbCBhY3RpdmUKbGFuZXMuCgpTaG91bGQgdWRwaHlfZHBfcGh5X3Nl dF92b2x0YWdlcygpIGNvbXB1dGUgdGhlIHZvbHRfY2ZnIGluZGV4IHBlciBsYW5lIHVzaW5nCmVh Y2ggbGFuZSdzIG93biBkcC0+dm9sdGFnZVtpXSBhbmQgZHAtPnByZVtpXSB2YWx1ZXMgc28gcGVy LWxhbmUgbGluayB0cmFpbmluZwphZGp1c3RtZW50cyBhcmUgYXBwbGllZD8KClsgLi4uIF0KCj4g K3N0YXRpYyBpbnQgdWRwaHlfZHBfcGh5X2NvbmZpZ3VyZShzdHJ1Y3QgcGh5ICpwaHksCj4gKwkJ CQkgIHVuaW9uIHBoeV9jb25maWd1cmVfb3B0cyAqb3B0cykKPiArewo+ICsJc3RydWN0IGNpeF91 ZHBoeSAqdWRwaHkgPSBwaHlfZ2V0X2RydmRhdGEocGh5KTsKPiArCWludCByZXQ7Cj4gKwo+ICsJ bXV0ZXhfbG9jaygmdWRwaHktPm11dGV4KTsKPiArCXJldCA9IHVkcGh5X2RwX3BoeV92ZXJpZnlf Y29uZmlnKHVkcGh5LCAmb3B0cy0+ZHApOwo+ICsJaWYgKHJldCkKPiArCQlnb3RvIHVubG9jazsK PiArCj4gKwlpZiAob3B0cy0+ZHAuc2V0X3JhdGUpIHsKPiArCQlyZXQgPSB1ZHBoeV9kcF9waHlf c2V0X3JhdGUodWRwaHksICZvcHRzLT5kcCk7Cj4gKwkJaWYgKHJldCkgewo+ICsJCQlkZXZfZXJy KHVkcGh5LT5kZXYsICJmYWlsZWQgdG8gc2V0IERQIGxpbmsgcmF0ZVxuIik7Cj4gKwkJCWdvdG8g dW5sb2NrOwo+ICsJCX0KPiArCX0KCltTZXZlcml0eTogSGlnaF0KV2hhdCBoYXBwZW5zIGlmIHVk cGh5X2RwX3BoeV9jb25maWd1cmUoKSBpcyBjYWxsZWQgd2hlbiBVRFBIWV9NT0RFX0RQIGlzIG5v dAphY3RpdmUgaW4gdWRwaHktPmN1cl9tb2RlLCBvciB3aXRoIG1vcmUgbGFuZXMgdGhhbiBhbGxv Y2F0ZWQgdG8gRFA/CgpJbiB1ZHBoeV9kcF9waHlfcG93ZXJfb24oKSwgaWYgISh1ZHBoeS0+bmV4 dF9tb2RlICYgVURQSFlfTU9ERV9EUCkgKGZvcgpleGFtcGxlIHdoZW4gVHlwZS1DIGlzIGluIFRZ UEVDX1NUQVRFX1NBRkUgb3IgVVNCLW9ubHkgbW9kZSwgb3Igd2hlbgpjaXgsZGVmYXVsdC1jb25m IGlzIDAgb3IgMSksIHVkcGh5X2RwX3BoeV9wb3dlcl9vbigpIHJldHVybnMgMCB3aXRob3V0CmVu YWJsaW5nIHVkcGh5LT5hcGJfY2xrIG9yIGRlYXNzZXJ0aW5nIHVkcGh5LT5wcmVzZXQuIEEgc3Vi c2VxdWVudCBjYWxsIHRvCnVkcGh5X2RwX3BoeV9jb25maWd1cmUoKSB3aWxsIHRoZW4gcGVyZm9y bSBNTUlPIHJlYWRzIGFuZCB3cml0ZXMgdGhyb3VnaAp1ZHBoeS0+cGh5X3JlZ21hcCB3aGlsZSB0 aGUgQVBCIGNsb2NrIGlzIGRpc2FibGVkIGFuZCBBUEIgcmVzZXQgaXMgYXNzZXJ0ZWQuCgpJbiBh ZGRpdGlvbiwgdWRwaHlfZHBfcGh5X3ZlcmlmeV9jb25maWcoKSBhY2NlcHRzIGRwLT5sYW5lcyA9 PSA0IHdpdGhvdXQKY2hlY2tpbmcgYWdhaW5zdCB1ZHBoeV9kcGxhbmVfZ2V0KHVkcGh5KSwgc28g YSA0LWxhbmUgRFAgY29uZmlndXJhdGlvbiBpbgoyLWxhbmUgVURQSFlfTU9ERV9EUF9VU0IgbW9k ZSB3aWxsIG92ZXJ3cml0ZSB0aGUgYWN0aXZlIFVTQiBsYW5lIHJlZ2lzdGVycyBpbgp1ZHBoeV9k cF9waHlfc2V0X3JhdGUoKSBhbmQgdWRwaHlfZHBfcGh5X3NldF92b2x0YWdlcygpLgoKLS0gClNh c2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2FzaGlrby5kZXYvIy9wYXRjaHNldC8yMDI2MTEw MjA4MjExMi4yMzA2MzI2LTEtZ2FyeS55YW5nQGNpeHRlY2guY29tP3BhcnQ9MwoKLS0gCmxpbnV4 LXBoeSBtYWlsaW5nIGxpc3QKbGludXgtcGh5QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cHM6Ly9s aXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcGh5Cg==