From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793617378; b=O/ALUkusdH0zQIa31rmNOTSo1WTIMxNB2/SjQoRDAqezWgm+3A6RPSXJZrjloeqcKNLs dtgWyJHRxN5WhMCtDJVsympCNyJETG4WfbF1TTHWa3EsR/nowAEzMnEKOcNBw4ePPnWqO NuK+2PoQs3D13FA441n7LB5nqPqeFi2SEB3yK0l757gQML6V7KBsHZqrALMvs4gbqT85T tvnvG3fDjNRePkSR0PYMaJ0cARmYT/CYoWjWh05EnSkzGcL7kRISJCT62PNAXR+golgDV zx46wmxOVPcCateeY6J7irfv7VnvadTX6aioT5JUKS/2CDx8NLrAkXcGm2cpBofg4Tg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793617378; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=CuPo69Bt2d/Z2NHIpCqclmwAPbn4rVhCPPDO1+/ROOc=; b=Ww+QuxobQr9iOKMjX0J7cz7BRg+m+fB7nn29IEefoXt8++kgnRwUiHBafwXwneHXKs95 hwjxitaSUHJyBMHo485hQKfgpGM34ETTeKA6NWz0CCKBhQKpWTW4P6eIdK3aeJhi1d4zp ug6oKfeiKpv9HwO03+oo1/9BcW7FX6sdUx+383RjQTb4lzFkcCVt61XP8awyqKiF4bobj OohB5nYdsIP5q+4pWr7aCgrkpL1b+Obq6hkN9Xsomdxpj3xNG9cTGJSJNG3JWwB6mBQCB ny283ei+LxnIKWoEwNV4ylHFVsjl5SbzYdukFQvrnLi/pGCYn5PzunC55qjyMcSrt4g== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=fCoq82Dj; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BA30606A324 for ; Mon, 2 Nov 2026 11:02:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=fCoq82Dj Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54F7F1F00A16; Mon, 2 Nov 2026 11:02:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793617377; bh=CuPo69Bt2d/Z2NHIpCqclmwAPbn4rVhCPPDO1+/ROOc=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=fCoq82Dj+epzxNNfzBmtUPNqc8RWFdMfOHBTkKVH9QDpgg3myKV8AiZEUYqy8MTYC CW2M/lRldCBrq0ERfdDcRfwEQCqjwFO/IxfzEoYcVpPnDLlK2kfx3f7nPtvXKoG+n9 /Ye8oY+mN+pwpl52ZHoWoNEvKrVVVpbVdpKEl6fFwFLGB2tW+8XmLXBL1oMdUicx/h Hx1p1ZuUb0EItcg07ay8FrXuh+nVGgOE5KGFRD18rtpNcTRIiNHQBFnUIoSbXC1MxB bvzeAJ9gBulK4//OdhUOSEejENAF2rTMaL9Xq2i0NbOL3lnsJ4HNy95Tlah5MXXGQo C8ScFweaxzzlg== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v24 09/15] media: qcom: camss: csid: Add support for CSID 1080 Reply-To: sashiko-reviews@lists.linux.dev To: "Hangxiang Ma" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, media-ci@linuxtv.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261102-kaanapali-camss-v24-9-d6b8f3f6f66f@oss.qualcomm.com> References: <20261102-kaanapali-camss-v24-0-d6b8f3f6f66f@oss.qualcomm.com> <20261102-kaanapali-camss-v24-9-d6b8f3f6f66f@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Mon, 02 Nov 2026 11:02:56 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 5 potential issue(= s) to consider: - [High] media: qcom: camss: unconditional AUP triggers in csid_configure_s= tream() - [Medium] media: qcom: camss: out-of-bounds csid->fmt access in __csid_con= figure_rdi_stream() - [Medium] media: qcom: camss: race on addr_update and reg_update in csid_i= sr() - [Low] media: qcom: camss: unused variable lane_cnt in __csid_configure_rd= i_stream() - [Low] media: qcom: camss: malformed kernel-doc Return sections in camss-c= sid-1080.c -- commit b46b9d6d26210a3faaa024307adfd55c2501ce00 Author: Hangxiang Ma media: qcom: camss: csid: Add support for CSID 1080 This commit adds hardware resource descriptions, register programming, reset handling, and interrupt support for the CSID 1080 module found on the Kaanapali SoC. > diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.c b/driver= s/media/platform/qcom/camss/camss-csid-1080.c > new file mode 100644 > index 0000000000000..3d90d31201fa5 > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-csid-1080.c > @@ -0,0 +1,402 @@ [ ... ] > +#define MSM_CSID_MAX_SRC_STREAMS_1080 (csid_is_lite(csid) ? 4 : 5) [ ... ] > +static void __csid_aup_rup_trigger(struct csid_device *csid) > +{ > + /* trigger SET in combined register */ > + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); > +} > + > +static void __csid_addr_update(struct csid_device *csid, int port_id) > +{ > + csid->addr_update |=3D CSID_RUP_AUP_RDI(port_id); > + writel(csid->addr_update, csid->base + CSID_AUP_CMD); > + > + __csid_aup_rup_trigger(csid); > +} > + > +static void __csid_addr_update_clear(struct csid_device *csid, int port_= id) > +{ > + csid->addr_update &=3D ~CSID_RUP_AUP_RDI(port_id); > +} > + > +static void __csid_reg_update(struct csid_device *csid, int port_id) > +{ > + csid->reg_update |=3D CSID_RUP_AUP_RDI(port_id); > + writel(csid->reg_update, csid->base + CSID_RUP_CMD); > + > + __csid_aup_rup_trigger(csid); > +} > + > +static void __csid_reg_update_clear(struct csid_device *csid, int port_i= d) > +{ > + csid->reg_update &=3D ~CSID_RUP_AUP_RDI(port_id); > +} [Severity: Medium] As reported by Sashiko on v14 [1], can concurrent updates to csid->addr_update and csid->reg_update race between process context and interrupt context? In __csid_addr_update(), __csid_addr_update_clear(), __csid_reg_update(), and __csid_reg_update_clear(), the bitmasks in csid->addr_update and csid->reg_update are modified with non-atomic |=3D and &=3D ~ operations, a= nd the full multi-port mask is written to CSID_AUP_CMD and CSID_RUP_CMD. While vfe_queue_buffer_v2() and vfe_enable_output_v2() invoke csid_subdev_addr_update() and csid_subdev_reg_update() under vfe->output_lock, csid_configure_stream() calls __csid_addr_update() and __csid_reg_update() without a lock, and csid_isr() clears those fields via __csid_addr_update_clear() and __csid_reg_update_clear() before camss_buf_done() acquires vfe->output_lock. In addition, within csid_isr(), camss_buf_done() is called for port i before higher-numbered RDI ports have had their INFO_RUP_DONE status checked and cleared in the loop, so a buffer update triggered from camss_buf_done() on port i can re-write CSID_AUP_CMD and CSID_RUP_CMD with stale bits still set for those higher-numbered ports. [ ... ] > +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 ena= ble, u8 port, u8 vc) > +{ > + u8 lane_cnt =3D csid->phy.lane_cnt; > + u32 val; > + > + /* Source pads matching RDI channels on hardware. > + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. > + */ > + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIR= ST_SRC + port]; > + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res-= >formats->formats, > + csid->res->formats->nformats, > + input_format->code); > + > + if (!lane_cnt) > + lane_cnt =3D 4; [Severity: Low] As reported by Sashiko on v23 [2], lane_cnt is initialized and updated in __csid_configure_rdi_stream(), but it is never read anywhere in the function. Will this trigger an unused-but-set-variable compiler warning? > + > + val =3D RDI_CFG0_TIMESTAMP_EN; > + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; > + val |=3D RDI_CFG0_RETIME_BS; > + > + /* note: for non-RDI path, this should be format->decode_format */ > + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; > + val |=3D vc << RDI_CFG0_VC; > + val |=3D format->data_type << RDI_CFG0_DT; > + writel(val, csid->base + CSID_RDI_CFG0(port)); > + > + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; > + writel(val, csid->base + CSID_RDI_CFG1(port)); > + > + /* Configure pixel store using dedicated register in 1080 */ > + if (!csid_is_lite(csid)) > + __csid_configure_rdi_pix_store(csid, port); > + > + val =3D 0; > + writel(val, csid->base + CSID_RDI_CTRL(port)); > + > + val =3D readl(csid->base + CSID_RDI_CFG0(port)); > + > + if (enable) > + val |=3D RDI_CFG0_EN; > + > + writel(val, csid->base + CSID_RDI_CFG0(port)); > +} > + > +static void csid_configure_stream(struct csid_device *csid, u8 enable) > +{ > + u8 i, k; > + > + __csid_configure_rx(csid, &csid->phy); > + > + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + __csid_configure_rdi_stream(csid, enable, i, 0); > + __csid_configure_rx_vc(csid, 0); [Severity: Medium] As reported by Sashiko on v14 [1], can __csid_configure_rdi_stream() index past the end of csid->fmt[] when i reaches 4? For non-lite CSID 1080 instances, MSM_CSID_MAX_SRC_STREAMS_1080 evaluates to 5, so csid_configure_stream() iterates i from 0 to 4 and passes i as port to __csid_configure_rdi_stream(): struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIR= ST_SRC + port]; However, in drivers/media/platform/qcom/camss/camss-csid.h, MSM_CSID_PAD_FIRST_SRC is 1 and MSM_CSID_PADS_NUM is 5 (1 sink pad and 4 source pads), sizing both csid->pads[MSM_CSID_PADS_NUM] and csid->fmt[MSM_CSID_PADS_NUM] to 5 elements (indices 0..4). When port is 4, MSM_CSID_PAD_FIRST_SRC + port evaluates to 5, which is one element past the end of csid->fmt[]. > + > + for (k =3D 0; k < CAMSS_INIT_BUF_COUNT; k++) > + __csid_addr_update(csid, i); > + > + __csid_reg_update(csid, i); [Severity: High] Does unconditionally calling __csid_addr_update() CAMSS_INIT_BUF_COUNT (2) times here match the buffers actually programmed in vfe_enable_output_v2()? During stream startup, vfe_enable_output_v2() in drivers/media/platform/qcom/camss/camss-vfe.c only calls ops->vfe_wm_update() for buffers actually present in the pending queue: for (i =3D 0; i < CAMSS_INIT_BUF_COUNT; i++) { output->buf[i] =3D vfe_buf_get_pending(output); if (!output->buf[i]) break; output->gen2.active_num++; ops->vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); if (!ops->addr_update) ops->reg_update(vfe, line->id); } If userspace starts streaming with 0 or 1 buffer queued (or when csid_configure_stream() is called with enable =3D=3D 0), csid_configure_stream() still triggers two AUPs and one RUP, which can latch uninitialized or duplicate WM buffer addresses into the hardware FIFO. Even when 2 buffers are queued prior to stream-on, vfe_enable_output_v2() writes both buffer addresses to the WM register before any AUP is issued. > + > + __csid_ctrl_rdi(csid, enable, i); > + } > + } > +} [ ... ] > +/** > + * csid_isr - CSID module interrupt service routine > + * @irq: Interrupt line > + * @dev: CSID device > + * > + * Return IRQ_HANDLED on success > + */ > +static irqreturn_t csid_isr(int irq, void *dev) > +{ [ ... ] > +} > + > +/** > + * csid_reset - Trigger reset on CSID module and wait to complete > + * @csid: CSID device > + * > + * Return 0 on success or a negative error code otherwise > + */ [Severity: Low] This isn't a bug, but the kernel-doc comments for csid_isr() and csid_reset() use "Return" instead of "Return:", which causes scripts/kernel-doc to warn about a missing return value description under W=3D1 builds. [1] https://lore.kernel.org/r/20260601162737.8D2531F00893@smtp.kernel.org [2] https://lore.kernel.org/r/20261028-kaanapali-camss-v23-9-95f250b18612@o= ss.qualcomm.com --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261102-kaanapali-= camss-v24-0-d6b8f3f6f66f@oss.qualcomm.com?part=3D9 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 545AF606A324 for ; Mon, 2 Nov 2026 11:03:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=HWTyj/+H; dkim=fail reason="signature verification failed" (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=fCoq82Dj DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Date:References: In-Reply-To:Cc:To:Subject:From:Message-ID:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Unsubscribe-Post:List-Owner; bh=yezTemgZ9l6a1ERrhnR1F89b/kL1FdMdV0M67Tc4hGA=; b=HWTyj/+HtYA84cy7U7Zx8x9CsP iLU/7Cm6j7Vx3HmNC8xYp4DaPZVJHkHc5s+TvF2MXAUx1wUS6VOKramNeGSRx4BicgJp0yG9PZ7LM rBk9GP6T+LJRjzLDDaDI9CZ4gqUJ6oZOFDLxbZpHU6QFxBSniazwkbjMJqA1C44D6WeDUWC+CgPkB lfvCSjVRXQKUjezZ1WiUAdJmkyh8msb0WRxAzubrSitxeSO6jvwdkVKoewL1gLNX0KKM5eVuJFyer gTCylNnb1XGaQeq6oIkYf2bZSgH6ZQh/UZUp07U+FOwfw9naBpILY/t9f/QjZfr9omDNqBpIHGYz9 MpQXzf0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xNpoa-0000000GFJr-0HZ3; Mon, 02 Nov 2026 11:03:00 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xNpoY-0000000GFJO-24Mw for linux-phy@lists.infradead.org; Mon, 02 Nov 2026 11:02:58 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id D67DE4177B; Mon, 2 Nov 2026 11:02:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54F7F1F00A16; Mon, 2 Nov 2026 11:02:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793617377; bh=CuPo69Bt2d/Z2NHIpCqclmwAPbn4rVhCPPDO1+/ROOc=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=fCoq82Dj+epzxNNfzBmtUPNqc8RWFdMfOHBTkKVH9QDpgg3myKV8AiZEUYqy8MTYC CW2M/lRldCBrq0ERfdDcRfwEQCqjwFO/IxfzEoYcVpPnDLlK2kfx3f7nPtvXKoG+n9 /Ye8oY+mN+pwpl52ZHoWoNEvKrVVVpbVdpKEl6fFwFLGB2tW+8XmLXBL1oMdUicx/h Hx1p1ZuUb0EItcg07ay8FrXuh+nVGgOE5KGFRD18rtpNcTRIiNHQBFnUIoSbXC1MxB bvzeAJ9gBulK4//OdhUOSEejENAF2rTMaL9Xq2i0NbOL3lnsJ4HNy95Tlah5MXXGQo C8ScFweaxzzlg== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v24 09/15] media: qcom: camss: csid: Add support for CSID 1080 To: "Hangxiang Ma" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, media-ci@linuxtv.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261102-kaanapali-camss-v24-9-d6b8f3f6f66f@oss.qualcomm.com> References: <20261102-kaanapali-camss-v24-0-d6b8f3f6f66f@oss.qualcomm.com> <20261102-kaanapali-camss-v24-9-d6b8f3f6f66f@oss.qualcomm.com> Date: Mon, 02 Nov 2026 11:02:56 +0000 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg NSBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIG1lZGlhOiBxY29tOiBj YW1zczogdW5jb25kaXRpb25hbCBBVVAgdHJpZ2dlcnMgaW4gY3NpZF9jb25maWd1cmVfc3RyZWFt KCkKLSBbTWVkaXVtXSBtZWRpYTogcWNvbTogY2Ftc3M6IG91dC1vZi1ib3VuZHMgY3NpZC0+Zm10 IGFjY2VzcyBpbiBfX2NzaWRfY29uZmlndXJlX3JkaV9zdHJlYW0oKQotIFtNZWRpdW1dIG1lZGlh OiBxY29tOiBjYW1zczogcmFjZSBvbiBhZGRyX3VwZGF0ZSBhbmQgcmVnX3VwZGF0ZSBpbiBjc2lk X2lzcigpCi0gW0xvd10gbWVkaWE6IHFjb206IGNhbXNzOiB1bnVzZWQgdmFyaWFibGUgbGFuZV9j bnQgaW4gX19jc2lkX2NvbmZpZ3VyZV9yZGlfc3RyZWFtKCkKLSBbTG93XSBtZWRpYTogcWNvbTog Y2Ftc3M6IG1hbGZvcm1lZCBrZXJuZWwtZG9jIFJldHVybiBzZWN0aW9ucyBpbiBjYW1zcy1jc2lk LTEwODAuYwotLQoKY29tbWl0IGI0NmI5ZDZkMjYyMTBhM2ZhYWEwMjQzMDdhZGZkNTVjMjUwMWNl MDAKQXV0aG9yOiBIYW5neGlhbmcgTWEgPGhhbmd4aWFuZy5tYUBvc3MucXVhbGNvbW0uY29tPgoK bWVkaWE6IHFjb206IGNhbXNzOiBjc2lkOiBBZGQgc3VwcG9ydCBmb3IgQ1NJRCAxMDgwCgpUaGlz IGNvbW1pdCBhZGRzIGhhcmR3YXJlIHJlc291cmNlIGRlc2NyaXB0aW9ucywgcmVnaXN0ZXIgcHJv Z3JhbW1pbmcsCnJlc2V0IGhhbmRsaW5nLCBhbmQgaW50ZXJydXB0IHN1cHBvcnQgZm9yIHRoZSBD U0lEIDEwODAgbW9kdWxlIGZvdW5kIG9uCnRoZSBLYWFuYXBhbGkgU29DLgoKPiBkaWZmIC0tZ2l0 IGEvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNzLWNzaWQtMTA4MC5jIGIv ZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNzLWNzaWQtMTA4MC5jCj4gbmV3 IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAwLi4zZDkwZDMxMjAxZmE1Cj4g LS0tIC9kZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0vcWNvbS9jYW1zcy9j YW1zcy1jc2lkLTEwODAuYwo+IEBAIC0wLDAgKzEsNDAyIEBACgpbIC4uLiBdCgo+ICsjZGVmaW5l IE1TTV9DU0lEX01BWF9TUkNfU1RSRUFNU18xMDgwCQkoY3NpZF9pc19saXRlKGNzaWQpID8gNCA6 IDUpCgpbIC4uLiBdCgo+ICtzdGF0aWMgdm9pZCBfX2NzaWRfYXVwX3J1cF90cmlnZ2VyKHN0cnVj dCBjc2lkX2RldmljZSAqY3NpZCkKPiArewo+ICsJLyogdHJpZ2dlciBTRVQgaW4gY29tYmluZWQg cmVnaXN0ZXIgKi8KPiArCXdyaXRlbChSVVBfU0VULCBjc2lkLT5iYXNlICsgQ1NJRF9SVVBfQVVQ X0NNRCk7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIF9fY3NpZF9hZGRyX3VwZGF0ZShzdHJ1Y3Qg Y3NpZF9kZXZpY2UgKmNzaWQsIGludCBwb3J0X2lkKQo+ICt7Cj4gKwljc2lkLT5hZGRyX3VwZGF0 ZSB8PSBDU0lEX1JVUF9BVVBfUkRJKHBvcnRfaWQpOwo+ICsJd3JpdGVsKGNzaWQtPmFkZHJfdXBk YXRlLCBjc2lkLT5iYXNlICsgQ1NJRF9BVVBfQ01EKTsKPiArCj4gKwlfX2NzaWRfYXVwX3J1cF90 cmlnZ2VyKGNzaWQpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBfX2NzaWRfYWRkcl91cGRhdGVf Y2xlYXIoc3RydWN0IGNzaWRfZGV2aWNlICpjc2lkLCBpbnQgcG9ydF9pZCkKPiArewo+ICsJY3Np ZC0+YWRkcl91cGRhdGUgJj0gfkNTSURfUlVQX0FVUF9SREkocG9ydF9pZCk7Cj4gK30KPiArCj4g K3N0YXRpYyB2b2lkIF9fY3NpZF9yZWdfdXBkYXRlKHN0cnVjdCBjc2lkX2RldmljZSAqY3NpZCwg aW50IHBvcnRfaWQpCj4gK3sKPiArCWNzaWQtPnJlZ191cGRhdGUgfD0gQ1NJRF9SVVBfQVVQX1JE SShwb3J0X2lkKTsKPiArCXdyaXRlbChjc2lkLT5yZWdfdXBkYXRlLCBjc2lkLT5iYXNlICsgQ1NJ RF9SVVBfQ01EKTsKPiArCj4gKwlfX2NzaWRfYXVwX3J1cF90cmlnZ2VyKGNzaWQpOwo+ICt9Cj4g Kwo+ICtzdGF0aWMgdm9pZCBfX2NzaWRfcmVnX3VwZGF0ZV9jbGVhcihzdHJ1Y3QgY3NpZF9kZXZp Y2UgKmNzaWQsIGludCBwb3J0X2lkKQo+ICt7Cj4gKwljc2lkLT5yZWdfdXBkYXRlICY9IH5DU0lE X1JVUF9BVVBfUkRJKHBvcnRfaWQpOwo+ICt9CgpbU2V2ZXJpdHk6IE1lZGl1bV0KQXMgcmVwb3J0 ZWQgYnkgU2FzaGlrbyBvbiB2MTQgWzFdLCBjYW4gY29uY3VycmVudCB1cGRhdGVzIHRvCmNzaWQt PmFkZHJfdXBkYXRlIGFuZCBjc2lkLT5yZWdfdXBkYXRlIHJhY2UgYmV0d2VlbiBwcm9jZXNzIGNv bnRleHQgYW5kCmludGVycnVwdCBjb250ZXh0PwoKSW4gX19jc2lkX2FkZHJfdXBkYXRlKCksIF9f Y3NpZF9hZGRyX3VwZGF0ZV9jbGVhcigpLCBfX2NzaWRfcmVnX3VwZGF0ZSgpLAphbmQgX19jc2lk X3JlZ191cGRhdGVfY2xlYXIoKSwgdGhlIGJpdG1hc2tzIGluIGNzaWQtPmFkZHJfdXBkYXRlIGFu ZApjc2lkLT5yZWdfdXBkYXRlIGFyZSBtb2RpZmllZCB3aXRoIG5vbi1hdG9taWMgfD0gYW5kICY9 IH4gb3BlcmF0aW9ucywgYW5kCnRoZSBmdWxsIG11bHRpLXBvcnQgbWFzayBpcyB3cml0dGVuIHRv IENTSURfQVVQX0NNRCBhbmQgQ1NJRF9SVVBfQ01ELgoKV2hpbGUgdmZlX3F1ZXVlX2J1ZmZlcl92 MigpIGFuZCB2ZmVfZW5hYmxlX291dHB1dF92MigpIGludm9rZQpjc2lkX3N1YmRldl9hZGRyX3Vw ZGF0ZSgpIGFuZCBjc2lkX3N1YmRldl9yZWdfdXBkYXRlKCkgdW5kZXIKdmZlLT5vdXRwdXRfbG9j aywgY3NpZF9jb25maWd1cmVfc3RyZWFtKCkgY2FsbHMgX19jc2lkX2FkZHJfdXBkYXRlKCkgYW5k Cl9fY3NpZF9yZWdfdXBkYXRlKCkgd2l0aG91dCBhIGxvY2ssIGFuZCBjc2lkX2lzcigpIGNsZWFy cyB0aG9zZSBmaWVsZHMgdmlhCl9fY3NpZF9hZGRyX3VwZGF0ZV9jbGVhcigpIGFuZCBfX2NzaWRf cmVnX3VwZGF0ZV9jbGVhcigpIGJlZm9yZQpjYW1zc19idWZfZG9uZSgpIGFjcXVpcmVzIHZmZS0+ b3V0cHV0X2xvY2suCgpJbiBhZGRpdGlvbiwgd2l0aGluIGNzaWRfaXNyKCksIGNhbXNzX2J1Zl9k b25lKCkgaXMgY2FsbGVkIGZvciBwb3J0IGkKYmVmb3JlIGhpZ2hlci1udW1iZXJlZCBSREkgcG9y dHMgaGF2ZSBoYWQgdGhlaXIgSU5GT19SVVBfRE9ORSBzdGF0dXMKY2hlY2tlZCBhbmQgY2xlYXJl ZCBpbiB0aGUgbG9vcCwgc28gYSBidWZmZXIgdXBkYXRlIHRyaWdnZXJlZCBmcm9tCmNhbXNzX2J1 Zl9kb25lKCkgb24gcG9ydCBpIGNhbiByZS13cml0ZSBDU0lEX0FVUF9DTUQgYW5kIENTSURfUlVQ X0NNRAp3aXRoIHN0YWxlIGJpdHMgc3RpbGwgc2V0IGZvciB0aG9zZSBoaWdoZXItbnVtYmVyZWQg cG9ydHMuCgpbIC4uLiBdCgo+ICtzdGF0aWMgdm9pZCBfX2NzaWRfY29uZmlndXJlX3JkaV9zdHJl YW0oc3RydWN0IGNzaWRfZGV2aWNlICpjc2lkLCB1OCBlbmFibGUsIHU4IHBvcnQsIHU4IHZjKQo+ ICt7Cj4gKwl1OCBsYW5lX2NudCA9IGNzaWQtPnBoeS5sYW5lX2NudDsKPiArCXUzMiB2YWw7Cj4g Kwo+ICsJLyogU291cmNlIHBhZHMgbWF0Y2hpbmcgUkRJIGNoYW5uZWxzIG9uIGhhcmR3YXJlLgo+ ICsJICogRS5nLiBQYWQgMSAtPiBSREkwLCBQYWQgMiAtPiBSREkxLCBldGMuCj4gKwkgKi8KPiAr CXN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQgKmlucHV0X2Zvcm1hdCA9ICZjc2lkLT5mbXRbTVNN X0NTSURfUEFEX0ZJUlNUX1NSQyArIHBvcnRdOwo+ICsJY29uc3Qgc3RydWN0IGNzaWRfZm9ybWF0 X2luZm8gKmZvcm1hdCA9IGNzaWRfZ2V0X2ZtdF9lbnRyeShjc2lkLT5yZXMtPmZvcm1hdHMtPmZv cm1hdHMsCj4gKwkJCQkJCQkJICAgY3NpZC0+cmVzLT5mb3JtYXRzLT5uZm9ybWF0cywKPiArCQkJ CQkJCQkgICBpbnB1dF9mb3JtYXQtPmNvZGUpOwo+ICsKPiArCWlmICghbGFuZV9jbnQpCj4gKwkJ bGFuZV9jbnQgPSA0OwoKW1NldmVyaXR5OiBMb3ddCkFzIHJlcG9ydGVkIGJ5IFNhc2hpa28gb24g djIzIFsyXSwgbGFuZV9jbnQgaXMgaW5pdGlhbGl6ZWQgYW5kIHVwZGF0ZWQgaW4KX19jc2lkX2Nv bmZpZ3VyZV9yZGlfc3RyZWFtKCksIGJ1dCBpdCBpcyBuZXZlciByZWFkIGFueXdoZXJlIGluIHRo ZQpmdW5jdGlvbi4gV2lsbCB0aGlzIHRyaWdnZXIgYW4gdW51c2VkLWJ1dC1zZXQtdmFyaWFibGUg Y29tcGlsZXIgd2FybmluZz8KCj4gKwo+ICsJdmFsID0gUkRJX0NGRzBfVElNRVNUQU1QX0VOOwo+ ICsJdmFsIHw9IFJESV9DRkcwX1RJTUVTVEFNUF9TVEJfU0VMOwo+ICsJdmFsIHw9IFJESV9DRkcw X1JFVElNRV9CUzsKPiArCj4gKwkvKiBub3RlOiBmb3Igbm9uLVJESSBwYXRoLCB0aGlzIHNob3Vs ZCBiZSBmb3JtYXQtPmRlY29kZV9mb3JtYXQgKi8KPiArCXZhbCB8PSBERUNPREVfRk9STUFUX1BB WUxPQURfT05MWSA8PCBSRElfQ0ZHMF9ERUNPREVfRk9STUFUOwo+ICsJdmFsIHw9IHZjIDw8IFJE SV9DRkcwX1ZDOwo+ICsJdmFsIHw9IGZvcm1hdC0+ZGF0YV90eXBlIDw8IFJESV9DRkcwX0RUOwo+ ICsJd3JpdGVsKHZhbCwgY3NpZC0+YmFzZSArIENTSURfUkRJX0NGRzAocG9ydCkpOwo+ICsKPiAr CXZhbCA9IFJESV9DRkcxX1BBQ0tJTkdfRk9STUFUX01JUEk7Cj4gKwl3cml0ZWwodmFsLCBjc2lk LT5iYXNlICsgQ1NJRF9SRElfQ0ZHMShwb3J0KSk7Cj4gKwo+ICsJLyogQ29uZmlndXJlIHBpeGVs IHN0b3JlIHVzaW5nIGRlZGljYXRlZCByZWdpc3RlciBpbiAxMDgwICovCj4gKwlpZiAoIWNzaWRf aXNfbGl0ZShjc2lkKSkKPiArCQlfX2NzaWRfY29uZmlndXJlX3JkaV9waXhfc3RvcmUoY3NpZCwg cG9ydCk7Cj4gKwo+ICsJdmFsID0gMDsKPiArCXdyaXRlbCh2YWwsIGNzaWQtPmJhc2UgKyBDU0lE X1JESV9DVFJMKHBvcnQpKTsKPiArCj4gKwl2YWwgPSByZWFkbChjc2lkLT5iYXNlICsgQ1NJRF9S RElfQ0ZHMChwb3J0KSk7Cj4gKwo+ICsJaWYgKGVuYWJsZSkKPiArCQl2YWwgfD0gUkRJX0NGRzBf RU47Cj4gKwo+ICsJd3JpdGVsKHZhbCwgY3NpZC0+YmFzZSArIENTSURfUkRJX0NGRzAocG9ydCkp Owo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBjc2lkX2NvbmZpZ3VyZV9zdHJlYW0oc3RydWN0IGNz aWRfZGV2aWNlICpjc2lkLCB1OCBlbmFibGUpCj4gK3sKPiArCXU4IGksIGs7Cj4gKwo+ICsJX19j c2lkX2NvbmZpZ3VyZV9yeChjc2lkLCAmY3NpZC0+cGh5KTsKPiArCj4gKwlmb3IgKGkgPSAwOyBp IDwgTVNNX0NTSURfTUFYX1NSQ19TVFJFQU1TXzEwODA7IGkrKykgewo+ICsJCWlmIChjc2lkLT5w aHkuZW5fdmMgJiBCSVQoaSkpIHsKPiArCQkJX19jc2lkX2NvbmZpZ3VyZV9yZGlfc3RyZWFtKGNz aWQsIGVuYWJsZSwgaSwgMCk7Cj4gKwkJCV9fY3NpZF9jb25maWd1cmVfcnhfdmMoY3NpZCwgMCk7 CgpbU2V2ZXJpdHk6IE1lZGl1bV0KQXMgcmVwb3J0ZWQgYnkgU2FzaGlrbyBvbiB2MTQgWzFdLCBj YW4gX19jc2lkX2NvbmZpZ3VyZV9yZGlfc3RyZWFtKCkgaW5kZXgKcGFzdCB0aGUgZW5kIG9mIGNz aWQtPmZtdFtdIHdoZW4gaSByZWFjaGVzIDQ/CgpGb3Igbm9uLWxpdGUgQ1NJRCAxMDgwIGluc3Rh bmNlcywgTVNNX0NTSURfTUFYX1NSQ19TVFJFQU1TXzEwODAgZXZhbHVhdGVzCnRvIDUsIHNvIGNz aWRfY29uZmlndXJlX3N0cmVhbSgpIGl0ZXJhdGVzIGkgZnJvbSAwIHRvIDQgYW5kIHBhc3NlcyBp IGFzCnBvcnQgdG8gX19jc2lkX2NvbmZpZ3VyZV9yZGlfc3RyZWFtKCk6CgogICAgc3RydWN0IHY0 bDJfbWJ1c19mcmFtZWZtdCAqaW5wdXRfZm9ybWF0ID0gJmNzaWQtPmZtdFtNU01fQ1NJRF9QQURf RklSU1RfU1JDICsgcG9ydF07CgpIb3dldmVyLCBpbiBkcml2ZXJzL21lZGlhL3BsYXRmb3JtL3Fj b20vY2Ftc3MvY2Ftc3MtY3NpZC5oLApNU01fQ1NJRF9QQURfRklSU1RfU1JDIGlzIDEgYW5kIE1T TV9DU0lEX1BBRFNfTlVNIGlzIDUgKDEgc2luayBwYWQgYW5kIDQKc291cmNlIHBhZHMpLCBzaXpp bmcgYm90aCBjc2lkLT5wYWRzW01TTV9DU0lEX1BBRFNfTlVNXSBhbmQKY3NpZC0+Zm10W01TTV9D U0lEX1BBRFNfTlVNXSB0byA1IGVsZW1lbnRzIChpbmRpY2VzIDAuLjQpLiBXaGVuIHBvcnQgaXMg NCwKTVNNX0NTSURfUEFEX0ZJUlNUX1NSQyArIHBvcnQgZXZhbHVhdGVzIHRvIDUsIHdoaWNoIGlz IG9uZSBlbGVtZW50IHBhc3QKdGhlIGVuZCBvZiBjc2lkLT5mbXRbXS4KCj4gKwo+ICsJCQlmb3Ig KGsgPSAwOyBrIDwgQ0FNU1NfSU5JVF9CVUZfQ09VTlQ7IGsrKykKPiArCQkJCV9fY3NpZF9hZGRy X3VwZGF0ZShjc2lkLCBpKTsKPiArCj4gKwkJCV9fY3NpZF9yZWdfdXBkYXRlKGNzaWQsIGkpOwoK W1NldmVyaXR5OiBIaWdoXQpEb2VzIHVuY29uZGl0aW9uYWxseSBjYWxsaW5nIF9fY3NpZF9hZGRy X3VwZGF0ZSgpIENBTVNTX0lOSVRfQlVGX0NPVU5UICgyKQp0aW1lcyBoZXJlIG1hdGNoIHRoZSBi dWZmZXJzIGFjdHVhbGx5IHByb2dyYW1tZWQgaW4gdmZlX2VuYWJsZV9vdXRwdXRfdjIoKT8KCkR1 cmluZyBzdHJlYW0gc3RhcnR1cCwgdmZlX2VuYWJsZV9vdXRwdXRfdjIoKSBpbgpkcml2ZXJzL21l ZGlhL3BsYXRmb3JtL3Fjb20vY2Ftc3MvY2Ftc3MtdmZlLmMgb25seSBjYWxscwpvcHMtPnZmZV93 bV91cGRhdGUoKSBmb3IgYnVmZmVycyBhY3R1YWxseSBwcmVzZW50IGluIHRoZSBwZW5kaW5nIHF1 ZXVlOgoKICAgIGZvciAoaSA9IDA7IGkgPCBDQU1TU19JTklUX0JVRl9DT1VOVDsgaSsrKSB7CiAg ICAgICAgb3V0cHV0LT5idWZbaV0gPSB2ZmVfYnVmX2dldF9wZW5kaW5nKG91dHB1dCk7CiAgICAg ICAgaWYgKCFvdXRwdXQtPmJ1ZltpXSkKICAgICAgICAgICAgYnJlYWs7CiAgICAgICAgb3V0cHV0 LT5nZW4yLmFjdGl2ZV9udW0rKzsKICAgICAgICBvcHMtPnZmZV93bV91cGRhdGUodmZlLCBvdXRw dXQtPndtX2lkeFswXSwKICAgICAgICAgICAgICAgICAgIG91dHB1dC0+YnVmW2ldLT5hZGRyWzBd LCBsaW5lKTsKICAgICAgICBpZiAoIW9wcy0+YWRkcl91cGRhdGUpCiAgICAgICAgICAgIG9wcy0+ cmVnX3VwZGF0ZSh2ZmUsIGxpbmUtPmlkKTsKICAgIH0KCklmIHVzZXJzcGFjZSBzdGFydHMgc3Ry ZWFtaW5nIHdpdGggMCBvciAxIGJ1ZmZlciBxdWV1ZWQgKG9yIHdoZW4KY3NpZF9jb25maWd1cmVf c3RyZWFtKCkgaXMgY2FsbGVkIHdpdGggZW5hYmxlID09IDApLApjc2lkX2NvbmZpZ3VyZV9zdHJl YW0oKSBzdGlsbCB0cmlnZ2VycyB0d28gQVVQcyBhbmQgb25lIFJVUCwgd2hpY2ggY2FuCmxhdGNo IHVuaW5pdGlhbGl6ZWQgb3IgZHVwbGljYXRlIFdNIGJ1ZmZlciBhZGRyZXNzZXMgaW50byB0aGUg aGFyZHdhcmUKRklGTy4gRXZlbiB3aGVuIDIgYnVmZmVycyBhcmUgcXVldWVkIHByaW9yIHRvIHN0 cmVhbS1vbiwKdmZlX2VuYWJsZV9vdXRwdXRfdjIoKSB3cml0ZXMgYm90aCBidWZmZXIgYWRkcmVz c2VzIHRvIHRoZSBXTSByZWdpc3RlcgpiZWZvcmUgYW55IEFVUCBpcyBpc3N1ZWQuCgo+ICsKPiAr CQkJX19jc2lkX2N0cmxfcmRpKGNzaWQsIGVuYWJsZSwgaSk7Cj4gKwkJfQo+ICsJfQo+ICt9Cgpb IC4uLiBdCgo+ICsvKioKPiArICogY3NpZF9pc3IgLSBDU0lEIG1vZHVsZSBpbnRlcnJ1cHQgc2Vy dmljZSByb3V0aW5lCj4gKyAqIEBpcnE6IEludGVycnVwdCBsaW5lCj4gKyAqIEBkZXY6IENTSUQg ZGV2aWNlCj4gKyAqCj4gKyAqIFJldHVybiBJUlFfSEFORExFRCBvbiBzdWNjZXNzCj4gKyAqLwo+ ICtzdGF0aWMgaXJxcmV0dXJuX3QgY3NpZF9pc3IoaW50IGlycSwgdm9pZCAqZGV2KQo+ICt7Cgpb IC4uLiBdCgo+ICt9Cj4gKwo+ICsvKioKPiArICogY3NpZF9yZXNldCAtIFRyaWdnZXIgcmVzZXQg b24gQ1NJRCBtb2R1bGUgYW5kIHdhaXQgdG8gY29tcGxldGUKPiArICogQGNzaWQ6IENTSUQgZGV2 aWNlCj4gKyAqCj4gKyAqIFJldHVybiAwIG9uIHN1Y2Nlc3Mgb3IgYSBuZWdhdGl2ZSBlcnJvciBj b2RlIG90aGVyd2lzZQo+ICsgKi8KCltTZXZlcml0eTogTG93XQpUaGlzIGlzbid0IGEgYnVnLCBi dXQgdGhlIGtlcm5lbC1kb2MgY29tbWVudHMgZm9yIGNzaWRfaXNyKCkgYW5kCmNzaWRfcmVzZXQo KSB1c2UgIlJldHVybiIgaW5zdGVhZCBvZiAiUmV0dXJuOiIsIHdoaWNoIGNhdXNlcwpzY3JpcHRz L2tlcm5lbC1kb2MgdG8gd2FybiBhYm91dCBhIG1pc3NpbmcgcmV0dXJuIHZhbHVlIGRlc2NyaXB0 aW9uIHVuZGVyClc9MSBidWlsZHMuCgpbMV0gaHR0cHM6Ly9sb3JlLmtlcm5lbC5vcmcvci8yMDI2 MDYwMTE2MjczNy44RDI1MzFGMDA4OTNAc210cC5rZXJuZWwub3JnClsyXSBodHRwczovL2xvcmUu a2VybmVsLm9yZy9yLzIwMjYxMDI4LWthYW5hcGFsaS1jYW1zcy12MjMtOS05NWYyNTBiMTg2MTJA b3NzLnF1YWxjb21tLmNvbQoKLS0gClNhc2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2FzaGlr by5kZXYvIy9wYXRjaHNldC8yMDI2MTEwMi1rYWFuYXBhbGktY2Ftc3MtdjI0LTAtZDZiOGYzZjZm NjZmQG9zcy5xdWFsY29tbS5jb20/cGFydD05CgotLSAKbGludXgtcGh5IG1haWxpbmcgbGlzdAps aW51eC1waHlAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwczovL2xpc3RzLmluZnJhZGVhZC5vcmcv bWFpbG1hbi9saXN0aW5mby9saW51eC1waHkK