Re: [PATCH v4 6/7] dmaengine: fsl-edma: support per-channel DT child nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dmaengine: fsl-edma: 64-bit modulo in fsl_edma_child_to_chan_id()
--

commit 76cf0654e1725c0e3aaa1017f35c2a7303b2f234
Author: Peng Fan <peng.fan@nxp.com>

dmaengine: fsl-edma: support per-channel DT child nodes

This commit adds support for parsing per-channel devicetree child nodes in
the fsl-edma driver to configure per-channel interrupts and IOMMU mappings.
It introduces helpers to derive the channel index from the child MMIO
address, obtain child interrupts before IRQ setup, and configure per-channel
IOMMUs after device registration.

> diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
> index 30d548a723462..8691676b3b692 100644
> --- a/drivers/dma/fsl-edma-main.c
> +++ b/drivers/dma/fsl-edma-main.c

[ ... ]

> @@ -703,6 +720,184 @@ static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_eng
>  	return -EINVAL;
>  }
>  
> +static int fsl_edma_child_to_chan_id(struct fsl_edma_engine *fsl_edma,
> +				     struct device_node *child,
> +				     struct resource *parent_res)
> +{
> +	const struct fsl_edma_drvdata *drvdata = fsl_edma->drvdata;
> +	struct resource child_res;
> +	u64 offset, ch_id;
> +	int ret;
> +
> +	ret = of_address_to_resource(child, 0, &child_res);
> +	if (ret)
> +		return ret;
> +
> +	if (!resource_contains(parent_res, &child_res))
> +		return -EINVAL;
> +
> +	if (child_res.start < parent_res->start + drvdata->chreg_off)
> +		return -EINVAL;
> +
> +	offset = child_res.start - parent_res->start - drvdata->chreg_off;
> +	if (offset % drvdata->chreg_space_sz)
> +		return -EINVAL;
> +
> +	ch_id = div_u64(offset, drvdata->chreg_space_sz);

[Severity: Medium]
As reported by kernel test robot on v3 [1], in fsl_edma_child_to_chan_id() in
drivers/dma/fsl-edma-main.c, offset is a u64 and drvdata->chreg_space_sz is a
u32. While the division uses div_u64(), evaluating offset %
drvdata->chreg_space_sz directly above it promotes drvdata->chreg_space_sz to
u64 and emits a 64-bit modulo library call (__umoddi3 or __aeabi_uldivmod),
which fails to link on 32-bit architectures when CONFIG_FSL_EDMA is enabled.

Could this use div_u64_rem(offset, drvdata->chreg_space_sz, &rem) to compute
both the alignment remainder and the channel ID quotient in a single step?

[1] https://lore.kernel.org/r/202611031650.EONIRpF4-lkp@intel.com

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261103-edma-iommu-v3-v4-0-470415d418c5@Example.Com?part=6