From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793736212; b=3lanrPbj3LZ9HTF7ckAYCWPFAoFyW2A8Auuwji+VRhoYB1/r8ZXlyOYN75bR10vuNetn LcwYUlTTct0k28+Y+23jCkAqH0gB64wZylhe/A4Tye6AwrY572t2McCLr5WWxZ+CT+5Al pW6l9rqzyXEleP1VqM2fGGocrp5r+DNY2nc7o+jH660kIuhIzJiihioNxyf6hlu5v7LWs KFoLhxi2N3ogYlnzkFpaBGBrNtFJLKgUIB+HDkmEfCzyTf0gwXpvTseazZivNDrIJYQag YjNlFcZioedFswDKmfYDfBY254xWa+aSIKWwtsiSkOY3WWI7deckQgqshWgbN/hYCAQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793736212; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=U1Or1ILmplwMCt9mtFKMvSlwMjG1et6SGTG6EtWHktk=; b=ofNpePizAr5y41PXG+WrYo7M+z6ybRYXwaE+vy5iwsL+MkMdZUhBsuX5ZtZZhNN9eub2 f5aPfGPGm5EtgHedOtqaGVjOe7x1v999Cml7vzRysJ4gfJnrZNZneaBi83edqKIWJKIC2 9uQ66IEcLJanZe+oujosQlRukJWLk9HmMhu4bus1ik5H2QF2/50tX6q2o93kfTuFDimxn /HMTqDP6aNBc/9y4FWygSRDkJva9yndCteGPAEF/magrTcOqY1LxKhy2JlSHdcPyvq51H G/iI9I0O+fCGYpA1Kn4r+A8Rf4c82nDluO4lAyyvqOQbbBrw6fjAWFsMqyJyGzP44Qg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=d7cYleg+; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CACC1606A326 for ; Tue, 3 Nov 2026 20:03:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=d7cYleg+ Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0993F1F0093A; Tue, 3 Nov 2026 20:03:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793736211; bh=U1Or1ILmplwMCt9mtFKMvSlwMjG1et6SGTG6EtWHktk=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=d7cYleg+OR4CIAZnd+7AnQG86/Zmdur8xmaMk55VXcxRpgKwhOo5CgjcvjGjXPTzU hlM8n0pvImC/lsaYnVM7wyp0wsZZpUzASyGuALKH95DdWNsE36h+AX5PfRvTD+y9Zc LgFdTwoznrd5iFfJUc/2E7lbjecno2ffy0jqJzOWENtxPpmrXFGBkO13y0i9Gy5dza bFBW2KKXf4CCLdiwLX9WAN1MZ8LlQxotDgU0BEzzZfnCI1sDFDATvBkFMQ5uGdrsNo pd65W0MKUQaO3Gn/nmp1JlCXGIQHyl8mjaPjutn+k95wDIAaIMyXpFmUvF2ur0bRsb dpzm+93yN6acw== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v5 2/2] phy: airoha: add support for AN7583 Gen3 PCIe PHY driver Reply-To: sashiko-reviews@lists.linux.dev To: "Christian Marangi" , linux-phy@lists.infradead.org, devicetree@vger.kernel.org Cc: robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261103195007.9721-3-ansuelsmth@gmail.com> References: <20261103195007.9721-1-ansuelsmth@gmail.com> <20261103195007.9721-3-ansuelsmth@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Tue, 03 Nov 2026 20:03:30 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 4 potential issue(= s) to consider: - [Medium] phy: airoha: use of devm_phy_optional_get() for required qp_phy - [Medium] phy: airoha: G3_ANA_PXP_JCPLL_SSC_EN not cleared on init or dein= it - [Low] phy: airoha: misuse of dev_err_probe() in an7583_pcie_phy_init() - [Low] phy: airoha: unused FREQ_LOCK_MAX_ATTEMPT macro and MAINTAINERS ord= er -- commit 2954f920d212f21a88edba191990e99091d7cd13 Author: Christian Marangi phy: airoha: add support for AN7583 Gen3 PCIe PHY driver This commit adds a new PHY driver for the Gen3 PCIe port on the Airoha AN7583 SoC, implementing its register map and calibration sequence. > diff --git a/MAINTAINERS b/MAINTAINERS > index 93abbb315065d..fb88a25ce0381 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -788,6 +788,14 @@ F: Documentation/devicetree/bindings/phy/airoha,en75= 81-pcie-phy.yaml > F: drivers/phy/phy-airoha-pcie-regs.h > F: drivers/phy/phy-airoha-pcie.c > =20 > +AIROHA AN7583 PCIE PHY DRIVER > +M: Christian Marangi > +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > +S: Maintained > +F: Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml > +F: drivers/phy/airoha/phy-an7583-pcie-regs.h > +F: drivers/phy/airoha/phy-an7583-pcie.c > + > AIROHA SOUND DRIVER > M: Christian Marangi > L: linux-sound@vger.kernel.org [ ... ] > diff --git a/drivers/phy/airoha/phy-an7583-pcie.c b/drivers/phy/airoha/ph= y-an7583-pcie.c > new file mode 100644 > index 0000000000000..f3c42654895f8 > --- /dev/null > +++ b/drivers/phy/airoha/phy-an7583-pcie.c > @@ -0,0 +1,823 @@ [ ... ] > +#include "phy-an7583-pcie-regs.h" > + > +#define FREQ_LOCK_MAX_ATTEMPT 50 [Severity: Low] This isn't a bug, but FREQ_LOCK_MAX_ATTEMPT is defined in drivers/phy/airoha/phy-an7583-pcie.c without being referenced anywhere in the driver. Also, in MAINTAINERS, AIROHA AN7583 PCIE PHY DRIVER is placed after AIROHA PCIE PHY DRIVER; should FREQ_LOCK_MAX_ATTEMPT be dropped and the MAINTAINERS entry be placed in alphabetical order before AIROHA ETHERNET DRIVER? [ ... ] > +static void an7583_pcie_phy_init_jcpll(struct an7583_pcie_phy *pcie_phy) > +{ > + regmap_set_bits(pcie_phy->g3_pma, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, > + G3_PMA_FORCE_SEL_DA_PXP_JCPLL_EN); > + regmap_clear_bits(pcie_phy->g3_pma, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, > + G3_PMA_FORCE_DA_PXP_JCPLL_EN); > + regmap_update_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SPARE_H, > + G3_ANA_PXP_JCPLL_SPARE_L, > + FIELD_PREP(G3_ANA_PXP_JCPLL_SPARE_L, 0x20)); > + regmap_set_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_RST_DLY, > + G3_ANA_PXP_JCPLL_PLL_RSTB); > + regmap_update_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SSC_DELTA, > + G3_ANA_PXP_JCPLL_SSC_DELTA, > + FIELD_PREP(G3_ANA_PXP_JCPLL_SSC_DELTA, 0x0)); > + regmap_update_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SSC_TRI_EN, > + G3_ANA_PXP_JCPLL_SSC_DELTA1, > + FIELD_PREP(G3_ANA_PXP_JCPLL_SSC_DELTA1, 0x0)); > + regmap_update_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SSC_DELTA, > + G3_ANA_PXP_JCPLL_SSC_PERIOD, > + FIELD_PREP(G3_ANA_PXP_JCPLL_SSC_PERIOD, 0x0)); > + regmap_clear_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_VCO_TCLVAR, > + G3_ANA_PXP_JCPLL_SSC_PHASE_INI); > + regmap_clear_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SSC_TRI_EN, > + G3_ANA_PXP_JCPLL_SSC_TRI_EN); [ ... ] > +static void an7583_pcie_phy_init_ssc_jcpll(struct an7583_pcie_phy *pcie_= phy) > +{ > + regmap_update_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SSC_DELTA, > + G3_ANA_PXP_JCPLL_SSC_DELTA, > + FIELD_PREP(G3_ANA_PXP_JCPLL_SSC_DELTA, 0x106)); > + regmap_update_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SSC_TRI_EN, > + G3_ANA_PXP_JCPLL_SSC_DELTA1, > + FIELD_PREP(G3_ANA_PXP_JCPLL_SSC_DELTA1, 0x106)); > + regmap_update_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SSC_DELTA, > + G3_ANA_PXP_JCPLL_SSC_PERIOD, > + FIELD_PREP(G3_ANA_PXP_JCPLL_SSC_PERIOD, 0x31B)); > + regmap_set_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_VCO_TCLVAR, > + G3_ANA_PXP_JCPLL_SSC_PHASE_INI); > + regmap_set_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_VCO_TCLVAR, > + G3_ANA_PXP_JCPLL_SSC_EN); > + regmap_set_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SDM_IFM, > + G3_ANA_PXP_JCPLL_SDM_IFM); > + regmap_set_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SDM_HREN, > + G3_ANA_PXP_JCPLL_SDM_HREN); > + regmap_clear_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_RST_DLY, > + G3_ANA_PXP_JCPLL_SDM_DI_EN); > + regmap_set_bits(pcie_phy->g3_ana, REG_PXP_JCPLL_SSC_TRI_EN, > + G3_ANA_PXP_JCPLL_SSC_TRI_EN); > +} [ ... ] > +static int an7583_pcie_phy_deinit(struct an7583_pcie_phy *pcie_phy) > +{ > + /* Disable RX CDR/PR */ > + regmap_clear_bits(pcie_phy->g3_pma, REG_SS_DA_XPON_PWDB_0, > + G3_PMA_DA_XPON_CDR_PR_PWDB); > + > + /* Disable TX PLL output/enable */ > + regmap_clear_bits(pcie_phy->g3_pma, REG_FORCE_DA_PXP_TXPLL_CKOUT_EN, > + G3_PMA_FORCE_DA_PXP_TXPLL_CKOUT_EN | > + G3_PMA_FORCE_SEL_DA_PXP_TXPLL_CKOUT_EN | > + G3_PMA_FORCE_SEL_DA_PXP_TXPLL_EN | > + G3_PMA_FORCE_DA_PXP_TXPLL_EN); > + > + /* Disable JCPLL output/enable */ > + regmap_clear_bits(pcie_phy->g3_pma, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, > + G3_PMA_FORCE_DA_PXP_JCPLL_CKOUT_EN | > + G3_PMA_FORCE_SEL_DA_PXP_JCPLL_CKOUT_EN | > + G3_PMA_FORCE_SEL_DA_PXP_JCPLL_EN | > + G3_PMA_FORCE_DA_PXP_JCPLL_EN); > + > + /* Assert PHY resets */ > + regmap_clear_bits(pcie_phy->g3_pma, REG_SW_RST_SET, > + G3_PMA_SW_TX_FIFO_RST_N | > + G3_PMA_SW_ALLPCS_RST_N | > + G3_PMA_SW_PMA_RST_N | > + G3_PMA_SW_TX_RST_N | > + G3_PMA_SW_RX_FIFO_RST_N | > + G3_PMA_SW_XFI_RXPCS_RST_N | > + G3_PMA_SW_REF_RST_N | > + G3_PMA_SW_RX_RST_N); > + > + /* Disable TX analog blocks */ > + regmap_clear_bits(pcie_phy->g3_ana, REG_PXP_TX_CKLDO_EN, > + G3_ANA_PXP_TX_CKLDO_EN | > + G3_ANA_PXP_TX_DMEDGEGEN_EN); > + > + return 0; > +} [Severity: Medium] When an7583_pcie_phy_init() runs, an7583_pcie_phy_init_ssc_jcpll() enables JCPLL spread-spectrum clocking by setting G3_ANA_PXP_JCPLL_SSC_PHASE_INI and G3_ANA_PXP_JCPLL_SSC_EN in REG_PXP_JCPLL_VCO_TCLVAR, and G3_ANA_PXP_JCPLL_SSC_TRI_EN in REG_PXP_JCPLL_SSC_TRI_EN. However, an7583_pcie_phy_deinit() does not clear these JCPLL SSC bits (in contrast to airoha_pcie_phy_exit() in drivers/phy/phy-airoha-pcie.c, which clears CSR_2L_PXP_JCPLL_SSC_PHASE_INI | CSR_2L_PXP_JCPLL_SSC_TRI_EN | CSR_2L_PXP_JCPLL_SSC_EN), and Phase 1 in an7583_pcie_phy_init_jcpll() only clears G3_ANA_PXP_JCPLL_SSC_PHASE_INI and G3_ANA_PXP_JCPLL_SSC_TRI_EN without clearing G3_ANA_PXP_JCPLL_SSC_EN. If the PHY is re-initialized after phy_exit() or after a failed phy_init() attempt (or if the bootloader left JCPLL SSC enabled), will G3_ANA_PXP_JCPLL_SSC_EN remain set during Phase 1 JCPLL and TXPLL configuration when SSC is supposed to be disabled? > + > +static int an7583_pcie_phy_init(struct phy *phy) > +{ [ ... ] > + ret =3D phy_init(pcie_phy->qp_phy); > + if (ret) { > + an7583_pcie_phy_deinit(pcie_phy); > + > + return dev_err_probe(pcie_phy->dev, ret, "failed to initialize QP phy\= n"); > + } [Severity: Low] Is dev_err_probe() appropriate inside the phy_ops .init callback an7583_pcie_phy_init()? Because an7583_pcie_phy_init() runs when a consumer PCIe controller driver calls phy_init() after an7583_pcie_phy_probe() has already bound pcie_phy->dev, calling dev_err_probe(pcie_phy->dev, ret, ...) will suppress error messages completely if ret is -ENOMEM, or downgrade the message to dev_dbg() and allocate pcie_phy->dev->p->deferred_probe_reason on an already-bound device if ret is -EPROBE_DEFER. Should this use dev_err() instead? [ ... ] > +static int an7583_pcie_phy_probe(struct platform_device *pdev) > +{ > + struct an7583_pcie_phy *pcie_phy; > + struct device *dev =3D &pdev->dev; > + struct phy_provider *provider; > + > + pcie_phy =3D devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL); > + if (!pcie_phy) > + return -ENOMEM; > + > + pcie_phy->g3_ana =3D an7583_pcie_phy_regmap_init(pdev, "g3-ana"); > + if (IS_ERR(pcie_phy->g3_ana)) > + return dev_err_probe(dev, PTR_ERR(pcie_phy->g3_ana), > + "Failed to initialize g3 ANA regmap\n"); > + > + pcie_phy->qp_phy =3D devm_phy_optional_get(dev, NULL); > + if (IS_ERR(pcie_phy->qp_phy)) > + return dev_err_probe(dev, PTR_ERR(pcie_phy->qp_phy), > + "Failed to get QP PCIe phy\n"); [Severity: Medium] Should an7583_pcie_phy_probe() use devm_phy_get() instead of devm_phy_optional_get() for pcie_phy->qp_phy? In Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml, phys is a required property because QPHY configuration is needed during the PCIe PHY setup and calibration phase. With devm_phy_optional_get(dev, NULL), a missing phys property or a disabled QPHY node in DeviceTree causes _of_phy_get() to return ERR_PTR(-ENODEV), which devm_phy_optional_get() turns into NULL. Both an7583_pcie_phy_probe() and phy_init(pcie_phy->qp_phy) in an7583_pcie_phy_init() will then succeed silently without initializing the required QPHY. --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261103195007.9721= -1-ansuelsmth@gmail.com?part=3D2 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B4BD606A31B for ; Tue, 3 Nov 2026 20:03:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=uYyxWhQJ; dkim=fail reason="signature verification failed" (2048-bit key, unprotected) header.d=kernel.org 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LgFdTwoznrd5iFfJUc/2E7lbjecno2ffy0jqJzOWENtxPpmrXFGBkO13y0i9Gy5dza bFBW2KKXf4CCLdiwLX9WAN1MZ8LlQxotDgU0BEzzZfnCI1sDFDATvBkFMQ5uGdrsNo pd65W0MKUQaO3Gn/nmp1JlCXGIQHyl8mjaPjutn+k95wDIAaIMyXpFmUvF2ur0bRsb dpzm+93yN6acw== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v5 2/2] phy: airoha: add support for AN7583 Gen3 PCIe PHY driver To: "Christian Marangi" , linux-phy@lists.infradead.org, devicetree@vger.kernel.org Cc: robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261103195007.9721-3-ansuelsmth@gmail.com> References: <20261103195007.9721-1-ansuelsmth@gmail.com> <20261103195007.9721-3-ansuelsmth@gmail.com> Date: Tue, 03 Nov 2026 20:03:30 +0000 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: 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Y29tbWl0IDI5NTRmOTIwZDIxMmYyMWE4OGVkYmExOTE5OTBlOTkwOTFkN2NkMTMKQXV0aG9yOiBD aHJpc3RpYW4gTWFyYW5naSA8YW5zdWVsc210aEBnbWFpbC5jb20+CgpwaHk6IGFpcm9oYTogYWRk IHN1cHBvcnQgZm9yIEFONzU4MyBHZW4zIFBDSWUgUEhZIGRyaXZlcgoKVGhpcyBjb21taXQgYWRk cyBhIG5ldyBQSFkgZHJpdmVyIGZvciB0aGUgR2VuMyBQQ0llIHBvcnQgb24gdGhlIEFpcm9oYQpB Tjc1ODMgU29DLCBpbXBsZW1lbnRpbmcgaXRzIHJlZ2lzdGVyIG1hcCBhbmQgY2FsaWJyYXRpb24g c2VxdWVuY2UuCgo+IGRpZmYgLS1naXQgYS9NQUlOVEFJTkVSUyBiL01BSU5UQUlORVJTCj4gaW5k ZXggOTNhYmJiMzE1MDY1ZC4uZmI4OGEyNWNlMDM4MSAxMDA2NDQKPiAtLS0gYS9NQUlOVEFJTkVS Uwo+ICsrKyBiL01BSU5UQUlORVJTCj4gQEAgLTc4OCw2ICs3ODgsMTQgQEAgRjoJRG9jdW1lbnRh dGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL3BoeS9haXJvaGEsZW43NTgxLXBjaWUtcGh5LnlhbWwK PiAgRjoJZHJpdmVycy9waHkvcGh5LWFpcm9oYS1wY2llLXJlZ3MuaAo+ICBGOglkcml2ZXJzL3Bo eS9waHktYWlyb2hhLXBjaWUuYwo+ICAKPiArQUlST0hBIEFONzU4MyBQQ0lFIFBIWSBEUklWRVIK PiArTToJQ2hyaXN0aWFuIE1hcmFuZ2kgPGFuc3VlbHNtdGhAZ21haWwuY29tPgo+ICtMOglsaW51 eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcgKG1vZGVyYXRlZCBmb3Igbm9uLXN1YnNj cmliZXJzKQo+ICtTOglNYWludGFpbmVkCj4gK0Y6CURvY3VtZW50YXRpb24vZGV2aWNldHJlZS9i aW5kaW5ncy9waHkvYWlyb2hhLGFuNzU4My1wY2llLWdlbjMtcGh5LnlhbWwKPiArRjoJZHJpdmVy cy9waHkvYWlyb2hhL3BoeS1hbjc1ODMtcGNpZS1yZWdzLmgKPiArRjoJZHJpdmVycy9waHkvYWly b2hhL3BoeS1hbjc1ODMtcGNpZS5jCj4gKwo+ICBBSVJPSEEgU09VTkQgRFJJVkVSCj4gIE06CUNo cmlzdGlhbiBNYXJhbmdpIDxhbnN1ZWxzbXRoQGdtYWlsLmNvbT4KPiAgTDoJbGludXgtc291bmRA dmdlci5rZXJuZWwub3JnClsgLi4uIF0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9waHkvYWlyb2hh L3BoeS1hbjc1ODMtcGNpZS5jIGIvZHJpdmVycy9waHkvYWlyb2hhL3BoeS1hbjc1ODMtcGNpZS5j Cj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAwLi5mM2M0MjY1NDg5 NWY4Cj4gLS0tIC9kZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvcGh5L2Fpcm9oYS9waHktYW43NTgz LXBjaWUuYwo+IEBAIC0wLDAgKzEsODIzIEBAClsgLi4uIF0KPiArI2luY2x1ZGUgInBoeS1hbjc1 ODMtcGNpZS1yZWdzLmgiCj4gKwo+ICsjZGVmaW5lIEZSRVFfTE9DS19NQVhfQVRURU1QVAk1MAoK W1NldmVyaXR5OiBMb3ddClRoaXMgaXNuJ3QgYSBidWcsIGJ1dCBGUkVRX0xPQ0tfTUFYX0FUVEVN UFQgaXMgZGVmaW5lZCBpbgpkcml2ZXJzL3BoeS9haXJvaGEvcGh5LWFuNzU4My1wY2llLmMgd2l0 aG91dCBiZWluZyByZWZlcmVuY2VkIGFueXdoZXJlIGluCnRoZSBkcml2ZXIuIEFsc28sIGluIE1B SU5UQUlORVJTLCBBSVJPSEEgQU43NTgzIFBDSUUgUEhZIERSSVZFUiBpcyBwbGFjZWQKYWZ0ZXIg QUlST0hBIFBDSUUgUEhZIERSSVZFUjsgc2hvdWxkIEZSRVFfTE9DS19NQVhfQVRURU1QVCBiZSBk cm9wcGVkIGFuZAp0aGUgTUFJTlRBSU5FUlMgZW50cnkgYmUgcGxhY2VkIGluIGFscGhhYmV0aWNh bCBvcmRlciBiZWZvcmUgQUlST0hBCkVUSEVSTkVUIERSSVZFUj8KClsgLi4uIF0KPiArc3RhdGlj IHZvaWQgYW43NTgzX3BjaWVfcGh5X2luaXRfamNwbGwoc3RydWN0IGFuNzU4M19wY2llX3BoeSAq cGNpZV9waHkpCj4gK3sKPiArCXJlZ21hcF9zZXRfYml0cyhwY2llX3BoeS0+ZzNfcG1hLCBSRUdf Rk9SQ0VfREFfUFhQX0pDUExMX0NLT1VUX0VOLAo+ICsJCQlHM19QTUFfRk9SQ0VfU0VMX0RBX1BY UF9KQ1BMTF9FTik7Cj4gKwlyZWdtYXBfY2xlYXJfYml0cyhwY2llX3BoeS0+ZzNfcG1hLCBSRUdf Rk9SQ0VfREFfUFhQX0pDUExMX0NLT1VUX0VOLAo+ICsJCQkgIEczX1BNQV9GT1JDRV9EQV9QWFBf SkNQTExfRU4pOwo+ICsJcmVnbWFwX3VwZGF0ZV9iaXRzKHBjaWVfcGh5LT5nM19hbmEsIFJFR19Q WFBfSkNQTExfU1BBUkVfSCwKPiArCQkJICAgRzNfQU5BX1BYUF9KQ1BMTF9TUEFSRV9MLAo+ICsJ CQkgICBGSUVMRF9QUkVQKEczX0FOQV9QWFBfSkNQTExfU1BBUkVfTCwgMHgyMCkpOwo+ICsJcmVn bWFwX3NldF9iaXRzKHBjaWVfcGh5LT5nM19hbmEsIFJFR19QWFBfSkNQTExfUlNUX0RMWSwKPiAr CQkJRzNfQU5BX1BYUF9KQ1BMTF9QTExfUlNUQik7Cj4gKwlyZWdtYXBfdXBkYXRlX2JpdHMocGNp ZV9waHktPmczX2FuYSwgUkVHX1BYUF9KQ1BMTF9TU0NfREVMVEEsCj4gKwkJCSAgIEczX0FOQV9Q WFBfSkNQTExfU1NDX0RFTFRBLAo+ICsJCQkgICBGSUVMRF9QUkVQKEczX0FOQV9QWFBfSkNQTExf U1NDX0RFTFRBLCAweDApKTsKPiArCXJlZ21hcF91cGRhdGVfYml0cyhwY2llX3BoeS0+ZzNfYW5h LCBSRUdfUFhQX0pDUExMX1NTQ19UUklfRU4sCj4gKwkJCSAgIEczX0FOQV9QWFBfSkNQTExfU1ND X0RFTFRBMSwKPiArCQkJICAgRklFTERfUFJFUChHM19BTkFfUFhQX0pDUExMX1NTQ19ERUxUQTEs IDB4MCkpOwo+ICsJcmVnbWFwX3VwZGF0ZV9iaXRzKHBjaWVfcGh5LT5nM19hbmEsIFJFR19QWFBf SkNQTExfU1NDX0RFTFRBLAo+ICsJCQkgICBHM19BTkFfUFhQX0pDUExMX1NTQ19QRVJJT0QsCj4g KwkJCSAgIEZJRUxEX1BSRVAoRzNfQU5BX1BYUF9KQ1BMTF9TU0NfUEVSSU9ELCAweDApKTsKPiAr CXJlZ21hcF9jbGVhcl9iaXRzKHBjaWVfcGh5LT5nM19hbmEsIFJFR19QWFBfSkNQTExfVkNPX1RD TFZBUiwKPiArCQkJICBHM19BTkFfUFhQX0pDUExMX1NTQ19QSEFTRV9JTkkpOwo+ICsJcmVnbWFw X2NsZWFyX2JpdHMocGNpZV9waHktPmczX2FuYSwgUkVHX1BYUF9KQ1BMTF9TU0NfVFJJX0VOLAo+ ICsJCQkgIEczX0FOQV9QWFBfSkNQTExfU1NDX1RSSV9FTik7ClsgLi4uIF0KPiArc3RhdGljIHZv aWQgYW43NTgzX3BjaWVfcGh5X2luaXRfc3NjX2pjcGxsKHN0cnVjdCBhbjc1ODNfcGNpZV9waHkg KnBjaWVfcGh5KQo+ICt7Cj4gKwlyZWdtYXBfdXBkYXRlX2JpdHMocGNpZV9waHktPmczX2FuYSwg UkVHX1BYUF9KQ1BMTF9TU0NfREVMVEEsCj4gKwkJCSAgIEczX0FOQV9QWFBfSkNQTExfU1NDX0RF TFRBLAo+ICsJCQkgICBGSUVMRF9QUkVQKEczX0FOQV9QWFBfSkNQTExfU1NDX0RFTFRBLCAweDEw NikpOwo+ICsJcmVnbWFwX3VwZGF0ZV9iaXRzKHBjaWVfcGh5LT5nM19hbmEsIFJFR19QWFBfSkNQ TExfU1NDX1RSSV9FTiwKPiArCQkJICAgRzNfQU5BX1BYUF9KQ1BMTF9TU0NfREVMVEExLAo+ICsJ CQkgICBGSUVMRF9QUkVQKEczX0FOQV9QWFBfSkNQTExfU1NDX0RFTFRBMSwgMHgxMDYpKTsKPiAr CXJlZ21hcF91cGRhdGVfYml0cyhwY2llX3BoeS0+ZzNfYW5hLCBSRUdfUFhQX0pDUExMX1NTQ19E RUxUQSwKPiArCQkJICAgRzNfQU5BX1BYUF9KQ1BMTF9TU0NfUEVSSU9ELAo+ICsJCQkgICBGSUVM RF9QUkVQKEczX0FOQV9QWFBfSkNQTExfU1NDX1BFUklPRCwgMHgzMUIpKTsKPiArCXJlZ21hcF9z ZXRfYml0cyhwY2llX3BoeS0+ZzNfYW5hLCBSRUdfUFhQX0pDUExMX1ZDT19UQ0xWQVIsCj4gKwkJ CUczX0FOQV9QWFBfSkNQTExfU1NDX1BIQVNFX0lOSSk7Cj4gKwlyZWdtYXBfc2V0X2JpdHMocGNp ZV9waHktPmczX2FuYSwgUkVHX1BYUF9KQ1BMTF9WQ09fVENMVkFSLAo+ICsJCQlHM19BTkFfUFhQ X0pDUExMX1NTQ19FTik7Cj4gKwlyZWdtYXBfc2V0X2JpdHMocGNpZV9waHktPmczX2FuYSwgUkVH X1BYUF9KQ1BMTF9TRE1fSUZNLAo+ICsJCQlHM19BTkFfUFhQX0pDUExMX1NETV9JRk0pOwo+ICsJ cmVnbWFwX3NldF9iaXRzKHBjaWVfcGh5LT5nM19hbmEsIFJFR19QWFBfSkNQTExfU0RNX0hSRU4s Cj4gKwkJCUczX0FOQV9QWFBfSkNQTExfU0RNX0hSRU4pOwo+ICsJcmVnbWFwX2NsZWFyX2JpdHMo cGNpZV9waHktPmczX2FuYSwgUkVHX1BYUF9KQ1BMTF9SU1RfRExZLAo+ICsJCQkgIEczX0FOQV9Q WFBfSkNQTExfU0RNX0RJX0VOKTsKPiArCXJlZ21hcF9zZXRfYml0cyhwY2llX3BoeS0+ZzNfYW5h LCBSRUdfUFhQX0pDUExMX1NTQ19UUklfRU4sCj4gKwkJCUczX0FOQV9QWFBfSkNQTExfU1NDX1RS SV9FTik7Cj4gK30KWyAuLi4gXQo+ICtzdGF0aWMgaW50IGFuNzU4M19wY2llX3BoeV9kZWluaXQo c3RydWN0IGFuNzU4M19wY2llX3BoeSAqcGNpZV9waHkpCj4gK3sKPiArCS8qIERpc2FibGUgUlgg Q0RSL1BSICovCj4gKwlyZWdtYXBfY2xlYXJfYml0cyhwY2llX3BoeS0+ZzNfcG1hLCBSRUdfU1Nf REFfWFBPTl9QV0RCXzAsCj4gKwkJCSAgRzNfUE1BX0RBX1hQT05fQ0RSX1BSX1BXREIpOwo+ICsK PiArCS8qIERpc2FibGUgVFggUExMIG91dHB1dC9lbmFibGUgKi8KPiArCXJlZ21hcF9jbGVhcl9i aXRzKHBjaWVfcGh5LT5nM19wbWEsIFJFR19GT1JDRV9EQV9QWFBfVFhQTExfQ0tPVVRfRU4sCj4g KwkJCSAgRzNfUE1BX0ZPUkNFX0RBX1BYUF9UWFBMTF9DS09VVF9FTiB8Cj4gKwkJCSAgRzNfUE1B X0ZPUkNFX1NFTF9EQV9QWFBfVFhQTExfQ0tPVVRfRU4gfAo+ICsJCQkgIEczX1BNQV9GT1JDRV9T RUxfREFfUFhQX1RYUExMX0VOIHwKPiArCQkJICBHM19QTUFfRk9SQ0VfREFfUFhQX1RYUExMX0VO KTsKPiArCj4gKwkvKiBEaXNhYmxlIEpDUExMIG91dHB1dC9lbmFibGUgKi8KPiArCXJlZ21hcF9j bGVhcl9iaXRzKHBjaWVfcGh5LT5nM19wbWEsIFJFR19GT1JDRV9EQV9QWFBfSkNQTExfQ0tPVVRf RU4sCj4gKwkJCSAgRzNfUE1BX0ZPUkNFX0RBX1BYUF9KQ1BMTF9DS09VVF9FTiB8Cj4gKwkJCSAg RzNfUE1BX0ZPUkNFX1NFTF9EQV9QWFBfSkNQTExfQ0tPVVRfRU4gfAo+ICsJCQkgIEczX1BNQV9G T1JDRV9TRUxfREFfUFhQX0pDUExMX0VOIHwKPiArCQkJICBHM19QTUFfRk9SQ0VfREFfUFhQX0pD UExMX0VOKTsKPiArCj4gKwkvKiBBc3NlcnQgUEhZIHJlc2V0cyAqLwo+ICsJcmVnbWFwX2NsZWFy X2JpdHMocGNpZV9waHktPmczX3BtYSwgUkVHX1NXX1JTVF9TRVQsCj4gKwkJCSAgRzNfUE1BX1NX X1RYX0ZJRk9fUlNUX04gfAo+ICsJCQkgIEczX1BNQV9TV19BTExQQ1NfUlNUX04gfAo+ICsJCQkg IEczX1BNQV9TV19QTUFfUlNUX04gfAo+ICsJCQkgIEczX1BNQV9TV19UWF9SU1RfTiB8Cj4gKwkJ CSAgRzNfUE1BX1NXX1JYX0ZJRk9fUlNUX04gfAo+ICsJCQkgIEczX1BNQV9TV19YRklfUlhQQ1Nf UlNUX04gfAo+ICsJCQkgIEczX1BNQV9TV19SRUZfUlNUX04gfAo+ICsJCQkgIEczX1BNQV9TV19S WF9SU1RfTik7Cj4gKwo+ICsJLyogRGlzYWJsZSBUWCBhbmFsb2cgYmxvY2tzICovCj4gKwlyZWdt YXBfY2xlYXJfYml0cyhwY2llX3BoeS0+ZzNfYW5hLCBSRUdfUFhQX1RYX0NLTERPX0VOLAo+ICsJ CQkgIEczX0FOQV9QWFBfVFhfQ0tMRE9fRU4gfAo+ICsJCQkgIEczX0FOQV9QWFBfVFhfRE1FREdF R0VOX0VOKTsKPiArCj4gKwlyZXR1cm4gMDsKPiArfQoKW1NldmVyaXR5OiBNZWRpdW1dCldoZW4g YW43NTgzX3BjaWVfcGh5X2luaXQoKSBydW5zLCBhbjc1ODNfcGNpZV9waHlfaW5pdF9zc2NfamNw bGwoKSBlbmFibGVzCkpDUExMIHNwcmVhZC1zcGVjdHJ1bSBjbG9ja2luZyBieSBzZXR0aW5nIEcz X0FOQV9QWFBfSkNQTExfU1NDX1BIQVNFX0lOSQphbmQgRzNfQU5BX1BYUF9KQ1BMTF9TU0NfRU4g aW4gUkVHX1BYUF9KQ1BMTF9WQ09fVENMVkFSLCBhbmQKRzNfQU5BX1BYUF9KQ1BMTF9TU0NfVFJJ X0VOIGluIFJFR19QWFBfSkNQTExfU1NDX1RSSV9FTi4KCkhvd2V2ZXIsIGFuNzU4M19wY2llX3Bo eV9kZWluaXQoKSBkb2VzIG5vdCBjbGVhciB0aGVzZSBKQ1BMTCBTU0MgYml0cyAoaW4KY29udHJh c3QgdG8gYWlyb2hhX3BjaWVfcGh5X2V4aXQoKSBpbiBkcml2ZXJzL3BoeS9waHktYWlyb2hhLXBj aWUuYywgd2hpY2gKY2xlYXJzIENTUl8yTF9QWFBfSkNQTExfU1NDX1BIQVNFX0lOSSB8IENTUl8y TF9QWFBfSkNQTExfU1NDX1RSSV9FTiB8CkNTUl8yTF9QWFBfSkNQTExfU1NDX0VOKSwgYW5kIFBo YXNlIDEgaW4gYW43NTgzX3BjaWVfcGh5X2luaXRfamNwbGwoKSBvbmx5CmNsZWFycyBHM19BTkFf UFhQX0pDUExMX1NTQ19QSEFTRV9JTkkgYW5kIEczX0FOQV9QWFBfSkNQTExfU1NDX1RSSV9FTgp3 aXRob3V0IGNsZWFyaW5nIEczX0FOQV9QWFBfSkNQTExfU1NDX0VOLgoKSWYgdGhlIFBIWSBpcyBy ZS1pbml0aWFsaXplZCBhZnRlciBwaHlfZXhpdCgpIG9yIGFmdGVyIGEgZmFpbGVkIHBoeV9pbml0 KCkKYXR0ZW1wdCAob3IgaWYgdGhlIGJvb3Rsb2FkZXIgbGVmdCBKQ1BMTCBTU0MgZW5hYmxlZCks IHdpbGwKRzNfQU5BX1BYUF9KQ1BMTF9TU0NfRU4gcmVtYWluIHNldCBkdXJpbmcgUGhhc2UgMSBK Q1BMTCBhbmQgVFhQTEwKY29uZmlndXJhdGlvbiB3aGVuIFNTQyBpcyBzdXBwb3NlZCB0byBiZSBk aXNhYmxlZD8KCj4gKwo+ICtzdGF0aWMgaW50IGFuNzU4M19wY2llX3BoeV9pbml0KHN0cnVjdCBw aHkgKnBoeSkKPiArewpbIC4uLiBdCj4gKwlyZXQgPSBwaHlfaW5pdChwY2llX3BoeS0+cXBfcGh5 KTsKPiArCWlmIChyZXQpIHsKPiArCQlhbjc1ODNfcGNpZV9waHlfZGVpbml0KHBjaWVfcGh5KTsK PiArCj4gKwkJcmV0dXJuIGRldl9lcnJfcHJvYmUocGNpZV9waHktPmRldiwgcmV0LCAiZmFpbGVk IHRvIGluaXRpYWxpemUgUVAgcGh5XG4iKTsKPiArCX0KCltTZXZlcml0eTogTG93XQpJcyBkZXZf ZXJyX3Byb2JlKCkgYXBwcm9wcmlhdGUgaW5zaWRlIHRoZSBwaHlfb3BzIC5pbml0IGNhbGxiYWNr CmFuNzU4M19wY2llX3BoeV9pbml0KCk/CgpCZWNhdXNlIGFuNzU4M19wY2llX3BoeV9pbml0KCkg cnVucyB3aGVuIGEgY29uc3VtZXIgUENJZSBjb250cm9sbGVyIGRyaXZlcgpjYWxscyBwaHlfaW5p dCgpIGFmdGVyIGFuNzU4M19wY2llX3BoeV9wcm9iZSgpIGhhcyBhbHJlYWR5IGJvdW5kCnBjaWVf cGh5LT5kZXYsIGNhbGxpbmcgZGV2X2Vycl9wcm9iZShwY2llX3BoeS0+ZGV2LCByZXQsIC4uLikg d2lsbCBzdXBwcmVzcwplcnJvciBtZXNzYWdlcyBjb21wbGV0ZWx5IGlmIHJldCBpcyAtRU5PTUVN LCBvciBkb3duZ3JhZGUgdGhlIG1lc3NhZ2UgdG8KZGV2X2RiZygpIGFuZCBhbGxvY2F0ZSBwY2ll X3BoeS0+ZGV2LT5wLT5kZWZlcnJlZF9wcm9iZV9yZWFzb24gb24gYW4KYWxyZWFkeS1ib3VuZCBk ZXZpY2UgaWYgcmV0IGlzIC1FUFJPQkVfREVGRVIuIFNob3VsZCB0aGlzIHVzZSBkZXZfZXJyKCkK aW5zdGVhZD8KClsgLi4uIF0KPiArc3RhdGljIGludCBhbjc1ODNfcGNpZV9waHlfcHJvYmUoc3Ry dWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ICsJc3RydWN0IGFuNzU4M19wY2llX3Bo eSAqcGNpZV9waHk7Cj4gKwlzdHJ1Y3QgZGV2aWNlICpkZXYgPSAmcGRldi0+ZGV2Owo+ICsJc3Ry dWN0IHBoeV9wcm92aWRlciAqcHJvdmlkZXI7Cj4gKwo+ICsJcGNpZV9waHkgPSBkZXZtX2t6YWxs b2MoZGV2LCBzaXplb2YoKnBjaWVfcGh5KSwgR0ZQX0tFUk5FTCk7Cj4gKwlpZiAoIXBjaWVfcGh5 KQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsKPiArCXBjaWVfcGh5LT5nM19hbmEgPSBhbjc1ODNf cGNpZV9waHlfcmVnbWFwX2luaXQocGRldiwgImczLWFuYSIpOwo+ICsJaWYgKElTX0VSUihwY2ll X3BoeS0+ZzNfYW5hKSkKPiArCQlyZXR1cm4gZGV2X2Vycl9wcm9iZShkZXYsIFBUUl9FUlIocGNp ZV9waHktPmczX2FuYSksCj4gKwkJCQkgICAgICJGYWlsZWQgdG8gaW5pdGlhbGl6ZSBnMyBBTkEg cmVnbWFwXG4iKTsKPiArCj4gKwlwY2llX3BoeS0+cXBfcGh5ID0gZGV2bV9waHlfb3B0aW9uYWxf Z2V0KGRldiwgTlVMTCk7Cj4gKwlpZiAoSVNfRVJSKHBjaWVfcGh5LT5xcF9waHkpKQo+ICsJCXJl dHVybiBkZXZfZXJyX3Byb2JlKGRldiwgUFRSX0VSUihwY2llX3BoeS0+cXBfcGh5KSwKPiArCQkJ CSAgICAgIkZhaWxlZCB0byBnZXQgUVAgUENJZSBwaHlcbiIpOwoKW1NldmVyaXR5OiBNZWRpdW1d ClNob3VsZCBhbjc1ODNfcGNpZV9waHlfcHJvYmUoKSB1c2UgZGV2bV9waHlfZ2V0KCkgaW5zdGVh ZCBvZgpkZXZtX3BoeV9vcHRpb25hbF9nZXQoKSBmb3IgcGNpZV9waHktPnFwX3BoeT8KCkluIERv Y3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9waHkvYWlyb2hhLGFuNzU4My1wY2llLWdl bjMtcGh5LnlhbWwsCnBoeXMgaXMgYSByZXF1aXJlZCBwcm9wZXJ0eSBiZWNhdXNlIFFQSFkgY29u ZmlndXJhdGlvbiBpcyBuZWVkZWQgZHVyaW5nIHRoZQpQQ0llIFBIWSBzZXR1cCBhbmQgY2FsaWJy YXRpb24gcGhhc2UuIFdpdGggZGV2bV9waHlfb3B0aW9uYWxfZ2V0KGRldiwgTlVMTCksCmEgbWlz c2luZyBwaHlzIHByb3BlcnR5IG9yIGEgZGlzYWJsZWQgUVBIWSBub2RlIGluIERldmljZVRyZWUg Y2F1c2VzCl9vZl9waHlfZ2V0KCkgdG8gcmV0dXJuIEVSUl9QVFIoLUVOT0RFViksIHdoaWNoIGRl dm1fcGh5X29wdGlvbmFsX2dldCgpCnR1cm5zIGludG8gTlVMTC4gQm90aCBhbjc1ODNfcGNpZV9w aHlfcHJvYmUoKSBhbmQgcGh5X2luaXQocGNpZV9waHktPnFwX3BoeSkKaW4gYW43NTgzX3BjaWVf cGh5X2luaXQoKSB3aWxsIHRoZW4gc3VjY2VlZCBzaWxlbnRseSB3aXRob3V0IGluaXRpYWxpemlu Zwp0aGUgcmVxdWlyZWQgUVBIWS4KCi0tIApTYXNoaWtvIEFJIHJldmlldyDCtyBodHRwczovL3Nh c2hpa28uZGV2LyMvcGF0Y2hzZXQvMjAyNjExMDMxOTUwMDcuOTcyMS0xLWFuc3VlbHNtdGhAZ21h aWwuY29tP3BhcnQ9MgoKLS0gCmxpbnV4LXBoeSBtYWlsaW5nIGxpc3QKbGludXgtcGh5QGxpc3Rz LmluZnJhZGVhZC5vcmcKaHR0cHM6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGlu Zm8vbGludXgtcGh5Cg==