Re: [PATCH 2/2] arm64: dts: qcom: sm8150: Use standalone ICE node for UFS

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] arm64: dts: qcom: sm8150: ufs_mem_hc violates qcom,ufs.yaml schema
--

commit 44282b2e2d420ebb8b4be7b6dd11cd5ecade575e
Author: Andrew Gigena <mail@andrewgigena.dev>

arm64: dts: qcom: sm8150: Use standalone ICE node for UFS

This commit converts the SM8150 UFS controller node to use a standalone
Inline Crypto Engine (ICE) node referenced via the qcom,ice property,
moving the ICE register region and clock out of ufs_mem_hc.

> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 293fcbacff346..b3d6f3d923950 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -2071,9 +2071,7 @@ pcie1_phy: phy@1c0e000 {
>  		ufs_mem_hc: ufshc@1d84000 {
>  			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
>  				     "jedec,ufs-2.0";
> -			reg = <0 0x01d84000 0 0x2500>,
> -			      <0 0x01d90000 0 0x8000>;
> -			reg-names = "std", "ice";
> +			reg = <0 0x01d84000 0 0x2500>;
>  			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>  			phys = <&ufs_mem_phy>;
>  			phy-names = "ufsphy";
> @@ -2092,8 +2090,7 @@ ufs_mem_hc: ufshc@1d84000 {
>  				"ref_clk",
>  				"tx_lane0_sync_clk",
>  				"rx_lane0_sync_clk",
> -				"rx_lane1_sync_clk",
> -				"ice_core_clk";
> +				"rx_lane1_sync_clk";
>  			clocks =
>  				<&gcc GCC_UFS_PHY_AXI_CLK>,
>  				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> @@ -2102,8 +2099,7 @@ ufs_mem_hc: ufshc@1d84000 {
>  				<&rpmhcc RPMH_CXO_CLK>,
>  				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>  				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> -				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
> -				<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> +				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>  			freq-table-hz =
>  				<37500000 300000000>,
>  				<0 0>,
> @@ -2112,8 +2108,8 @@ ufs_mem_hc: ufshc@1d84000 {
>  				<0 0>,
>  				<0 0>,
>  				<0 0>,
> -				<0 0>,
> -				<0 300000000>;
> +				<0 0>;
> +			qcom,ice = <&ice>;

[Severity: Low]
Does converting ufs_mem_hc here without updating the devicetree binding
cause dtbs_check failures on SM8150 and SA8155P boards?

In Documentation/devicetree/bindings/ufs/qcom,ufs.yaml, the allOf entry
matching qcom,sm8150-ufshc still requires 9 clocks (including
ice_core_clk), 2 reg entries, and reg-names:

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm845-ufshc
              - qcom,sm6350-ufshc
              - qcom,sm8150-ufshc
    then:
      properties:
        clocks:
          minItems: 9
          maxItems: 9
        clock-names:
          items:
            ...
            - const: ice_core_clk
        reg:
          minItems: 2
        reg-names:
          minItems: 2
      required:
        - reg-names

Meanwhile, the rule for qcom,ice in the same binding requires maxItems: 1
for reg and maxItems: 8 for clocks, which conflicts with the
qcom,sm8150-ufshc constraints above.

Should qcom,sm8150-ufshc be updated in the UFS binding schema (for example,
moved to Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
alongside qcom,sm8250-ufshc and qcom,sm8450-ufshc) before or along with
this change?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104-sm8150-ice-rfc-v1-0-5737b6c2ecc0@andrewgigena.dev?part=2