From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 378C9606D802 for ; Wed, 4 Nov 2026 11:43:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=VagtUoAY; dkim=fail reason="signature verification failed" (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=AlG3bo64 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Date:References: In-Reply-To:Cc:To:Subject:From:Message-ID:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Unsubscribe-Post:List-Owner; bh=e5bWMhVFA67Qo6ez81bbD7q52HT6+P4YJW8e8AVToco=; b=VagtUoAYlFkF3xWr7dMu6xtcXH 6+YOgnhbLDNEt+nvp5dnP0uDTkYQZA/Evq/tui/rD6X5WGqD1B0A+xPCU2c8HpcvbjwQ4WKO0CFLN oofa3BCv56/HyJxcD7VuukkzNZNNw7F6hvvIVqKbnzB+sOf/gmBNl2ZU3oi4ins8vUiSOPy1DepCO yzBt5dvf1nTSC7lL7W6qcKM2OaB5UwKa8nJrXj2yMfpZeTqiN2OSoqioT2SfiXTe+ryBx4ehjajmD m8e0uiW6YG64folnUFDncnJhawo5o5Z1as1xikXtsOE+AeLhHnppliuX/awkgRadirtMJLivfAqj1 toxC40aQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xOZPF-00000005DLd-43gV; Wed, 04 Nov 2026 11:43:53 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xOZPF-00000005DLT-0WRF for linux-i3c@lists.infradead.org; Wed, 04 Nov 2026 11:43:53 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id AD0A940B4F; Wed, 4 Nov 2026 11:43:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 440591F000C1; Wed, 4 Nov 2026 11:43:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793792632; bh=CS23nMGiYphLe/0ej6egsSAB2f8i8m7h8S/Y9UHFc0I=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=AlG3bo64TkwY/7W+PxQLU6vpw6d4VdFu2xw5IUNg/tN6csdAQSB17w/v+lDRmwsR3 hrpwp+2uO0dyQolroXYKA9CeDn6IuR9txmVDg3Cs7jjPAb3O/ARzraPlgGVSD6YKt8 zYKp3OjrWaTfKdNK01tIA02AiefN4wf2PuSN2SSvjkpZEjn8/YozuO0p58OOwUkEBX JHz0xcZ0ng0ztB8PJNpX/66Zg/R+StH4JIFM5FxQsmvpDVMK1B8yq4eaPeKbcf/kSW smNAtM7lFUkqV6DnClqz6ZcftiAhQTNAQUW0IYWq7YRX3YdjwRrWXkzbClgA2amNUm bu0H2itBNPgxA== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v7 2/3] i3c: master: Add Qualcomm I3C controller driver To: "Mukesh Kumar Savaliya" , linux-i3c@lists.infradead.org, devicetree@vger.kernel.org Cc: robh@kernel.org, conor+dt@kernel.org, Frank.Li@kernel.org, "Alexandre Belloni" In-Reply-To: <20261104111610.3739095-2-mukesh.savaliya@oss.qualcomm.com> References: <20261104111610.3739095-1-mukesh.savaliya@oss.qualcomm.com> <20261104111610.3739095-2-mukesh.savaliya@oss.qualcomm.com> Date: Wed, 04 Nov 2026 11:43:51 +0000 X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-i3c" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MTAgcG90ZW50aWFsIGlzc3VlKHMpIHRvIGNvbnNpZGVyOgotIFtIaWdoXSBpM2M6IHFjb20tZ2Vu aTogdXNlXzdlIHVwZGF0ZWQgYWZ0ZXIgbV9wYXJhbSBpbiBnZW5pX2kzY19tYXN0ZXJfcHJpdl94 ZmVycygpCi0gW0hpZ2hdIGkzYzogcWNvbS1nZW5pOiBicm9rZW4gSTNDX0FERFJfTUFTSyBhbmQg REFBIGhhbmRsaW5nIGluIGdlbmlfaTNjX3BlcmZvcm1fZGFhKCkKLSBbSGlnaF0gaTNjOiBxY29t LWdlbmk6IGludmFsaWQgY2xvY2sgbG9va3VwIGFuZCAxIE1IeiBjeWNsZSBjb3VudCBpbiBnZW5p X2kzY19jbGtfbWFwCi0gW0hpZ2hdIGkzYzogcWNvbS1nZW5pOiB1bnNhZmUgSTJDIERNQSBtYXBw aW5nIGFuZCBicm9rZW4gRE1BIHJlc2V0IGhhbmRsaW5nCi0gW0hpZ2hdIGkzYzogcWNvbS1nZW5p OiBicm9rZW4gc2hvcnQgUlggRklGTyByZWFkcyBhbmQgZWFybHkgdGVybWluYXRpb24gaW4gZ2Vu aV9pM2NfaXJxKCkKLSBbSGlnaF0gaTNjOiBxY29tLWdlbmk6IE5BQ0sgZXJyb3Igb3ZlcndyaXRl IGFuZCBzdGF0dXMgYml0bWFzayBtaXNtYXRjaCBpbiBnZW5pX2kzY19oYW5kbGVfZXJyKCkKLSBb SGlnaF0gaTNjOiBxY29tLWdlbmk6IG1pc3NpbmcgcmVpbml0X2NvbXBsZXRpb24oKSBhbmQgVFhf UkVTRVRfRE9ORSBpbiBfaTNjX2dlbmlfZXhlY3V0ZV9jb21tYW5kKCkKLSBbSGlnaF0gaTNjOiBx Y29tLWdlbmk6IFRYIHdhdGVybWFyayByYWNlIGFuZCB1bmhhbmRsZWQgSVJRIHN0b3JtIGluIGdl bmlfaTNjX2lycSgpCi0gW01lZGl1bV0gaTNjOiBxY29tLWdlbmk6IGRvdWJsZSBnZW5pX3NlX3Jl c291cmNlc19vZmYoKSBjYWxsIGluIGdlbmlfaTNjX3Byb2JlKCkKLSBbTG93XSBpM2M6IHFjb20t Z2VuaTogdW51c2VkIHZhcmlhYmxlIG1fc3RhdF9tYXNrIGluIGdlbmlfaTNjX2lycSgpCi0tCgpj b21taXQgMmFkMTVlNjAyNDZjZDc4OTgyMDVmNDMxZDk4YWJiN2UwNTNkMmQ5NwpBdXRob3I6IE11 a2VzaCBLdW1hciBTYXZhbGl5YSA8bXVrZXNoLnNhdmFsaXlhQG9zcy5xdWFsY29tbS5jb20+Cgpp M2M6IG1hc3RlcjogQWRkIFF1YWxjb21tIEkzQyBjb250cm9sbGVyIGRyaXZlcgoKVGhpcyBjb21t aXQgYWRkcyBhIGRyaXZlciBmb3IgdGhlIFF1YWxjb21tIFFVUHYzIEdFTkktYmFzZWQgSTNDIG1h c3Rlcgpjb250cm9sbGVyIHN1cHBvcnRpbmcgSTNDIFNEUiBhbmQgbGVnYWN5IEkyQyB0cmFuc2Zl cnMuCgo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2kzYy9tYXN0ZXIvaTNjLXFjb20tZ2VuaS5jIGIv ZHJpdmVycy9pM2MvbWFzdGVyL2kzYy1xY29tLWdlbmkuYwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0 Cj4gaW5kZXggMDAwMDAwMDAwMDAwMC4uMmZlZTc3ZTY4MWUyNgo+IC0tLSAvZGV2L251bGwKPiAr KysgYi9kcml2ZXJzL2kzYy9tYXN0ZXIvaTNjLXFjb20tZ2VuaS5jClsgLi4uIF0KPiArI2RlZmlu ZSBJM0NfQVVUT19TVVNQRU5EX0RFTEFZCTI1MAo+ICsjZGVmaW5lIFBBQ0tJTkdfQllURVNfUEVS X1dPUkQJNAo+ICsjZGVmaW5lIFhGRVJfVElNRU9VVAkJMjUwCj4gKwo+ICsjZGVmaW5lIEkzQ19B RERSX01BU0sJCShJMkNfTUFYX0FERFIgPj4gMSkKWyAuLi4gXQo+ICtzdHJ1Y3QgZ2VuaV9pM2Nf ZGV2IHsKWyAuLi4gXQo+ICsJdTggKmN1cl9idWY7Cj4gKwl1OCBsYXN0X2FkZHI7Cj4gKwlib29s IGN1cl9pc193cml0ZTsKPiArCWludCBjdXJfbGVuOwo+ICsJaW50IGN1cl9pZHg7Cj4gKwlERUNM QVJFX0JJVE1BUChuZXdhZGRyc2xvdHMsIDY0KTsKPiArCj4gKwljb25zdCBzdHJ1Y3QgZ2VuaV9p M2NfY2xrX3NldHRpbmdzICpjbGtfY2ZnOwo+ICsJY29uc3Qgc3RydWN0IGdlbmlfaTNjX2Nsa19z ZXR0aW5ncyAqY2xrX29kX2NmZzsKPiArfTsKCltTZXZlcml0eTogSGlnaF0KU2luY2UgSTJDX01B WF9BRERSIGlzIGRlZmluZWQgYXMgR0VOTUFTSyg2LCAwKSAoMHg3ZikgaW4KaW5jbHVkZS9saW51 eC9pM2MvbWFzdGVyLmgsIHNoaWZ0aW5nIGl0IHJpZ2h0IGJ5IDEgbWFrZXMgSTNDX0FERFJfTUFT SyAweDNmCig2IGJpdHMgaW5zdGVhZCBvZiA3IGJpdHMpLCBhbmQgbmV3YWRkcnNsb3RzIGlzIG9u bHkgNjQgYml0cyB3aWRlIGluc3RlYWQgb2YKSTNDX01BWF9BRERSICsgMSAoMTI4KS4KCkxhdGVy IGluIGdlbmlfaTNjX3BlcmZvcm1fZGFhKCk6CgoJYWRkciA9IGkzY19tYXN0ZXJfZ2V0X2ZyZWVf YWRkcigmZ2kzYy0+Y3RybHIsCgkJCQkJZ2kzYy0+bGFzdF9hZGRyICsgMSk7CglpZiAoYWRkciA+ IEkzQ19BRERSX01BU0spCgkJcmV0dXJuIC1FSU5WQUw7CgoJZ2kzYy0+bGFzdF9hZGRyID0gYWRk cjsKCXNldF9iaXQoYWRkciwgZ2kzYy0+bmV3YWRkcnNsb3RzKTsKCS4uLgoJcmV0ID0gaTNjX2dl bmlfZXhlY3V0ZV93cml0ZV9jb21tYW5kKGdpM2MsICZ4ZmVyLCB0eF9idWYsIDEpOwoJaWYgKHJl dCkKCQlicmVhazsKCkRvZXNuJ3QgdGhpcyByZWplY3QgdmFsaWQgNy1iaXQgZHluYW1pYyBhZGRy ZXNzZXMgZnJvbSAweDQwIHRvIDB4N2QgKGFzIHdlbGwKYXMgdHJ1bmNhdGluZyBuZWdhdGl2ZSBl cnJvciBjb2RlcyBmcm9tIGkzY19tYXN0ZXJfZ2V0X2ZyZWVfYWRkcigpIGludG8gdTgpPwoKQWxz bywgaW4gZ2VuaV9pM2NfcGVyZm9ybV9kYWEoKSBhbmQgZ2VuaV9pM2NfbWFzdGVyX3NlbmRfY2Nj X2NtZCgpOgotIGdpM2MtPmxhc3RfYWRkciBpcyBuZXZlciByZXNldCBiZXR3ZWVuIERBQSBydW5z LCBzbyByZXBlYXRlZCBEQUEKICBpbnZvY2F0aW9ucyB3aWxsIG9ubHkgc2VhcmNoIGFib3ZlIHRo ZSBwcmV2aW91cyBhZGRyZXNzIHVudGlsIHRoZSByYW5nZSBpcwogIGV4aGF1c3RlZC4KLSBzZXRf Yml0KGFkZHIsIGdpM2MtPm5ld2FkZHJzbG90cykgaXMgY2FsbGVkIGJlZm9yZQogIGkzY19nZW5p X2V4ZWN1dGVfd3JpdGVfY29tbWFuZCgpIHNlbmRzIHRoZSBkeW5hbWljIGFkZHJlc3MgdG8gdGhl IHRhcmdldC4KICBJZiB0aGF0IHdyaXRlIGZhaWxzLCBnZW5pX2kzY19wZXJmb3JtX2RhYSgpIGJy ZWFrcyBvdXQgYW5kIHJldHVybnMgMCB3aXRoCiAgYWRkciBzdGlsbCBzZXQgaW4gbmV3YWRkcnNs b3RzLCBjYXVzaW5nIGdlbmlfaTNjX21hc3Rlcl9kb19kYWEoKSB0byBjYWxsCiAgaTNjX21hc3Rl cl9hZGRfaTNjX2Rldl9sb2NrZWQoKSBmb3IgYW4gdW5hc3NpZ25lZCBhZGRyZXNzLgotIGdlbmlf aTNjX21hc3Rlcl9zZW5kX2NjY19jbWQoKSBpZ25vcmVzIHRoZSByZXR1cm4gdmFsdWUgb2YKICBn ZW5pX2kzY19wZXJmb3JtX2RhYShnaTNjKS4KClNob3VsZCBJM0NfQUREUl9NQVNLIGJlIEkzQ19N QVhfQUREUiAoMHg3Zikgd2l0aCBuZXdhZGRyc2xvdHMgc2l6ZWQgdG8KSTNDX01BWF9BRERSICsg MSwgYW5kIHNob3VsZCBzZXRfYml0KGFkZHIsIGdpM2MtPm5ld2FkZHJzbG90cykgaGFwcGVuIG9u bHkKYWZ0ZXIgdGhlIGFkZHJlc3Mgd3JpdGUgc3VjY2VlZHM/CgpbIC4uLiBdCj4gK3N0YXRpYyBj b25zdCBzdHJ1Y3QgZ2VuaV9pM2NfY2xrX3NldHRpbmdzIGdlbmlfaTNjX2Nsa19tYXBbXSA9IHsK PiArCXsKPiArCQkuY2xrX2ZyZXFfb3V0ID0gMTAwICogSFpfUEVSX0tIWiwKPiArCQkuY2xrX3Ny Y19mcmVxID0gMTkyMDAgKiBIWl9QRVJfS0haLAo+ICsJCS5jbGtfZGl2ID0gMSwKPiArCQkuaTJj X3RfaGlnaF9jbnQgPSA3NiwKPiArCQkuaTJjX3RfbG93X2NudCA9IDkwLAo+ICsJCS5pM2NfdF9o aWdoX2NudCA9IDcsCj4gKwkJLmkzY190X2N5Y2xlX2NudCA9IDgsCj4gKwkJLmkyY190X2N5Y2xl X2NudCA9IDE5MiwKPiArCX0sCj4gKwl7Cj4gKwkJLmNsa19mcmVxX291dCA9IDQwMCAqIEhaX1BF Ul9LSFosCj4gKwkJLmNsa19zcmNfZnJlcSA9IDE5MjAwICogSFpfUEVSX0tIWiwKPiArCQkuY2xr X2RpdiA9IDEsCj4gKwkJLmkyY190X2hpZ2hfY250ID0gMTIsCj4gKwkJLmkyY190X2xvd19jbnQg PSAyNCwKPiArCQkuaTNjX3RfaGlnaF9jbnQgPSA3LAo+ICsJCS5pM2NfdF9jeWNsZV9jbnQgPSA4 LAo+ICsJCS5pMmNfdF9jeWNsZV9jbnQgPSA0OAo+ICsJfSwKPiArCXsKPiArCQkuY2xrX2ZyZXFf b3V0ID0gMTAwMCAqIEhaX1BFUl9LSFosCj4gKwkJLmNsa19zcmNfZnJlcSA9IDE5MjAwICogSFpf UEVSX0tIWiwKPiArCQkuY2xrX2RpdiA9IDEsCj4gKwkJLmkyY190X2hpZ2hfY250ID0gNCwKPiAr CQkuaTJjX3RfbG93X2NudCA9IDksCj4gKwkJLmkzY190X2hpZ2hfY250ID0gNywKPiArCQkuaTNj X3RfY3ljbGVfY250ID0gMCwKPiArCQkuaTJjX3RfY3ljbGVfY250ID0gMTkKPiArCX0sCj4gKwl7 Cj4gKwkJLmNsa19mcmVxX291dCA9IDEyNTAwICogSFpfUEVSX0tIWiwKPiArCQkuY2xrX3NyY19m cmVxID0gMTAwMDAwICogSFpfUEVSX0tIWiwKPiArCQkuY2xrX2RpdiA9IDEsCj4gKwkJLmkyY190 X2hpZ2hfY250ID0gNDUsCj4gKwkJLmkyY190X2xvd19jbnQgPSA2MywKPiArCQkuaTNjX3RfaGln aF9jbnQgPSA2LAo+ICsJCS5pM2NfdF9jeWNsZV9jbnQgPSA3LAo+ICsJCS5pMmNfdF9jeWNsZV9j bnQgPSAxMTAKPiArCX0KPiArfTsKPiArCj4gK3N0YXRpYyBpbnQgZ2VuaV9pM2NfY2xrX21hcF9p ZHgoc3RydWN0IGdlbmlfaTNjX2RldiAqZ2kzYykKPiArewo+ICsJY29uc3Qgc3RydWN0IGdlbmlf aTNjX2Nsa19zZXR0aW5ncyAqY2xrX3RhYmxlX2lkeCA9IGdlbmlfaTNjX2Nsa19tYXA7Cj4gKwlz dHJ1Y3QgaTNjX21hc3Rlcl9jb250cm9sbGVyICptID0gJmdpM2MtPmN0cmxyOwo+ICsJc3RydWN0 IGkzY19idXMgKmJ1cyA9IGkzY19tYXN0ZXJfZ2V0X2J1cyhtKTsKPiArCj4gKwlmb3IgKGludCBp ID0gMDsgaSA8IEFSUkFZX1NJWkUoZ2VuaV9pM2NfY2xrX21hcCk7IGkrKywgY2xrX3RhYmxlX2lk eCsrKSB7Cj4gKwkJaWYgKGNsa190YWJsZV9pZHgtPmNsa19mcmVxX291dCA9PSBidXMtPnNjbF9y YXRlLmkzYyAmJgo+ICsJCSAgICBjbGtfdGFibGVfaWR4LT5jbGtfc3JjX2ZyZXEgPT0gZ2kzYy0+ Y2xrX3NyY19mcmVxKQo+ICsJCQlnaTNjLT5jbGtfY2ZnID0gY2xrX3RhYmxlX2lkeDsKPiArCj4g KwkJaWYgKGNsa190YWJsZV9pZHgtPmNsa19mcmVxX291dCA9PSBidXMtPnNjbF9yYXRlLmkyYykK PiArCQkJZ2kzYy0+Y2xrX29kX2NmZyA9IGNsa190YWJsZV9pZHg7Cj4gKwl9Cj4gKwo+ICsJaWYg KCFnaTNjLT5jbGtfY2ZnIHx8ICFnaTNjLT5jbGtfb2RfY2ZnKQo+ICsJCXJldHVybiAtRUlOVkFM Owo+ICsKPiArCXJldHVybiAwOwo+ICt9CgpbU2V2ZXJpdHk6IEhpZ2hdCkhvdyBkb2VzIGdlbmlf aTNjX2Nsa19tYXBfaWR4KCkgYmVoYXZlIG9uIGEgcHVyZSBJM0MgYnVzIG9yIGEgbWl4ZWQtc2xv dwpidXM/CgpJbiBpM2NfYnVzX3NldF9tb2RlKCksIHdoZW4gYnVzLT5tb2RlIGlzIEkzQ19CVVNf TU9ERV9QVVJFIGFuZCBubyBpMmMtc2NsLWh6CnByb3BlcnR5IGlzIHNldCBpbiBkZXZpY2V0cmVl LCBidXMtPnNjbF9yYXRlLmkyYyByZW1haW5zIDAuIEJlY2F1c2Ugbm8gZW50cnkKaW4gZ2VuaV9p M2NfY2xrX21hcFtdIGhhcyBjbGtfZnJlcV9vdXQgPT0gMCwgZ2kzYy0+Y2xrX29kX2NmZyBzdGF5 cyBOVUxMIGFuZApnZW5pX2kzY19tYXN0ZXJfYnVzX2luaXQoKSBmYWlscyB3aXRoIC1FSU5WQUwu CgpDb252ZXJzZWx5LCBpbiBJM0NfQlVTX01PREVfTUlYRURfU0xPVyAod2hlcmUgaTNjX2J1c19z ZXRfbW9kZSgpIGNsYW1wcwpidXMtPnNjbF9yYXRlLmkzYyB0byBidXMtPnNjbF9yYXRlLmkyYyks IGkzY19nZW5pX3Jlc291cmNlc19pbml0KCkgaGFyZGNvZGVzCmdpM2MtPmNsa19zcmNfZnJlcSB0 byAxMDAgTUh6IHdoaWxlIHRoZSAxMDAga0h6LCA0MDAga0h6LCBhbmQgMTAwMCBrSHoKZW50cmll cyBpbiBnZW5pX2kzY19jbGtfbWFwW10gYWxsIGhhdmUgY2xrX3NyY19mcmVxIHNldCB0byAxOS4y IE1Ieiwgc28KZ2kzYy0+Y2xrX2NmZyBzdGF5cyBOVUxMIGFuZCBnZW5pX2kzY19jbGtfbWFwX2lk eCgpIGFsc28gcmV0dXJucyAtRUlOVkFMLgoKQWxzbywgaW4gdGhlIDEwMDAga0h6IGVudHJ5IG9m IGdlbmlfaTNjX2Nsa19tYXBbXSwgaTNjX3RfY3ljbGVfY250IGlzIDAgd2hpbGUKaTNjX3RfaGln aF9jbnQgaXMgNyAod2hlcmVhcyB0aGUgMTAwIGtIeiBhbmQgNDAwIGtIeiBlbnRyaWVzIHVzZQpp M2NfdF9jeWNsZV9jbnQgPSA4KS4gSXMgcHJvZ3JhbW1pbmcgU0VfSTNDX1NDTF9DWUNMRSB0byAw IHdoZW4KcWNvbV9nZW5pX2kzY19jb25mKGdpM2MsIE9QRU5fRFJBSU5fTU9ERSkgc2VsZWN0cyB0 aGUgMTAwMCBrSHogZW50cnkKaW50ZW50aW9uYWw/CgpbIC4uLiBdCj4gK3N0YXRpYyB2b2lkIGdl bmlfaTNjX2hhbmRsZV9lcnIoc3RydWN0IGdlbmlfaTNjX2RldiAqZ2kzYywgdTMyIHN0YXR1cykK PiArewo+ICsJZGV2X2RiZyhnaTNjLT5zZS5kZXYsICJsZW46JWQsICVzXG4iLAo+ICsJCWdpM2Mt PmN1cl9sZW4sIGdpM2MtPmN1cl9pc193cml0ZSA/ICJ3cml0ZSIgOiAicmVhZCIpOwo+ICsKPiAr CWlmIChzdGF0dXMgJiBNX0dQX0lSUV8wX0VOKSB7Cj4gKwkJZ2kzYy0+ZXJyID0gLUVJTlZBTDsK PiArCQlkZXZfZGJnKGdpM2MtPnNlLmRldiwgIkkzQyBzbGF2ZSBlYXJseSByZWFkIHRlcm1pbmF0 aW9uXG4iKTsKPiArCX0KWyAuLi4gXQo+ICsJaWYgKHN0YXR1cyAmIE1fQ01EX0FCT1JUX0VOKSB7 Cj4gKwkJZ2kzYy0+ZXJyID0gLUVUSU1FRE9VVDsKPiArCQlkZXZfZGJnKGdpM2MtPnNlLmRldiwg IkFib3J0IGFmdGVyIHRpbWVvdXQgc3VjY2Vzc2Z1bFxuIik7Cj4gKwl9Cj4gKwo+ICsJaWYgKHN0 YXR1cyA9PSBHRU5JX1RJTUVPVVQpIHsKPiArCQlnaTNjLT5lcnIgPSAtRVRJTUVET1VUOwo+ICsJ CWRldl9kYmcoZ2kzYy0+c2UuZGV2LCAiSTNDIHRyYW5zYWN0aW9uIHRpbWVkIG91dFxuIik7Cj4g Kwl9Cj4gK30KCltTZXZlcml0eTogSGlnaF0KV29uJ3QgZ2VuaV9pM2NfaGFuZGxlX2VycigpIGNs b2JiZXIgYW4gZWFybGllciBOQUNLIGVycm9yICgtRU5PVENPTk4gb3IKLUVCVVNZKSB3aXRoIC1F VElNRURPVVQgd2hlbiBhIHRyYW5zZmVyIHRpbWVzIG91dCBhbmQgYWJvcnRzPwoKV2hlbiBhIE5B Q0sgaW50ZXJydXB0IGZpcmVzIHdpdGhvdXQgTV9DTURfRE9ORV9FTiBzZXQsIGdlbmlfaTNjX2ly cSgpIHJlY29yZHMKLUVOT1RDT05OIG9yIC1FQlVTWSBpbiBnaTNjLT5lcnIgYW5kIHdhaXRzIGZv ciB0aGUgdGltZW91dCBwYXRoIGluCl9pM2NfZ2VuaV9leGVjdXRlX2NvbW1hbmQoKSB0byBhYm9y dCB0aGUgY29tbWFuZC4gQm90aCB0aGUgdGltZW91dCBwYXRoCihwYXNzaW5nIEdFTklfVElNRU9V VCkgYW5kIHRoZSBzdWJzZXF1ZW50IE1fQ01EX0FCT1JUX0VOIGludGVycnVwdCBvdmVyd3JpdGUK Z2kzYy0+ZXJyIHdpdGggLUVUSU1FRE9VVCwgc28gZ2VuaV9pM2NfbWFzdGVyX3NlbmRfY2NjX2Nt ZCgpIG5vIGxvbmdlciBzZWVzCi1FTk9UQ09OTiBvciAtRUJVU1kgYW5kIGNhbm5vdCBzZXQgY21k LT5lcnIgPSBJM0NfRVJST1JfTTIuCgpJbiBhZGRpdGlvbiwgc3RhdHVzIGluIGdlbmlfaTNjX2hh bmRsZV9lcnIoKSBpcyBjaGVja2VkIGJvdGggYXMgYW4KU0VfR0VOSV9NX0lSUV9TVEFUVVMgYml0 bWFzayBhbmQgZm9yIGVxdWFsaXR5IHdpdGggdGhlIGVudW0gY29uc3RhbnQKR0VOSV9USU1FT1VU ICh3aGljaCBoYXMgdmFsdWUgOSwgb3IgTV9DTURfRkFJTFVSRV9FTiB8IE1fQ01EX0RPTkVfRU4p LiBBbmQKaWYgZ2VuaV9pM2NfaXJxKCkgZW50ZXJzIHRoZSBlcnJvciBicmFuY2ggZHVlIHRvIGRt X3J4X3N0ICYgRE1fSTNDX0NCX0VSUiBvcgpNX0NNRF9GQUlMVVJFX0VOIGFsb25lLCBnZW5pX2kz Y19oYW5kbGVfZXJyKGdpM2MsIG1fc3RhdCkgbGVhdmVzIGdpM2MtPmVyciBhcwowLiBTaG91bGQg Z2kzYy0+ZXJyIG9ubHkgYmUgdXBkYXRlZCB3aGVuIGl0IGlzIG5vdCBhbHJlYWR5IHNldCwgd2l0 aCBhCmZhbGxiYWNrIGVycm9yIGNvZGUgd2hlbiBub25lIG9mIHRoZSBzcGVjaWZpYyBNX0dQX0lS UV8qIGJpdHMgbWF0Y2g/Cgo+ICsKPiArc3RhdGljIGlycXJldHVybl90IGdlbmlfaTNjX2lycShp bnQgaXJxLCB2b2lkICpkZXYpCj4gK3sKPiArCXN0cnVjdCBnZW5pX2kzY19kZXYgKmdpM2MgPSBk ZXY7Cj4gKwl1MzIgbV9zdGF0X21hc2ssIGRtX3R4X3N0LCBkbV9yeF9zdDsKPiArCXUzMiBtX3N0 YXQsIHJ4X3N0LCBkbWFfbW9kZTsKPiArCj4gKwltX3N0YXQgPSByZWFkbF9yZWxheGVkKGdpM2Mt PnNlLmJhc2UgKyBTRV9HRU5JX01fSVJRX1NUQVRVUyk7Cj4gKwltX3N0YXRfbWFzayA9IHJlYWRs X3JlbGF4ZWQoZ2kzYy0+c2UuYmFzZSArIFNFX0dFTklfTV9JUlFfRU4pOwoKW1NldmVyaXR5OiBM b3ddCkluIGdlbmlfaTNjX2lycSgpLCBtX3N0YXRfbWFzayBpcyBhc3NpZ25lZCBoZXJlIGJ1dCBu ZXZlciB1c2VkLCB3aGljaCB3aWxsCnRyaWdnZXIgYW4gdW51c2VkLWJ1dC1zZXQtdmFyaWFibGUg Y29tcGlsZXIgd2FybmluZy4gU2hvdWxkIG1fc3RhdCBiZSBtYXNrZWQKd2l0aCBtX3N0YXRfbWFz aywgb3Igc2hvdWxkIG1fc3RhdF9tYXNrIGJlIHJlbW92ZWQ/Cgo+ICsJcnhfc3QgPSByZWFkbF9y ZWxheGVkKGdpM2MtPnNlLmJhc2UgKyBTRV9HRU5JX1JYX0ZJRk9fU1RBVFVTKTsKPiArCWRtX3R4 X3N0ID0gcmVhZGxfcmVsYXhlZChnaTNjLT5zZS5iYXNlICsgU0VfRE1BX1RYX0lSUV9TVEFUKTsK PiArCWRtX3J4X3N0ID0gcmVhZGxfcmVsYXhlZChnaTNjLT5zZS5iYXNlICsgU0VfRE1BX1JYX0lS UV9TVEFUKTsKPiArCWRtYV9tb2RlID0gcmVhZGxfcmVsYXhlZChnaTNjLT5zZS5iYXNlICsgU0Vf R0VOSV9ETUFfTU9ERV9FTik7Cj4gKwo+ICsJc2NvcGVkX2d1YXJkKHNwaW5sb2NrLCAmZ2kzYy0+ aXJxX2xvY2spIHsKPiArCQlpZiAobV9zdGF0ICYgU0VfSTNDX0VSUiB8fCBkbV9yeF9zdCAmIERN X0kzQ19DQl9FUlIpIHsKPiArCQkJZ2VuaV9pM2NfaGFuZGxlX2VycihnaTNjLCBtX3N0YXQpOwo+ ICsJCQkvKiBEaXNhYmxlIHRoZSBUWCBXYXRlcm1hcmsgaW50ZXJydXB0IHRvIHN0b3AgVFggKi8K PiArCQkJaWYgKCFkbWFfbW9kZSkKPiArCQkJCXdyaXRlbF9yZWxheGVkKDAsIGdpM2MtPnNlLmJh c2UgKyBTRV9HRU5JX1RYX1dBVEVSTUFSS19SRUcpOwo+ICsJCX0gZWxzZSBpZiAoZG1hX21vZGUp IHsKPiArCQkJZGV2X2RiZyhnaTNjLT5zZS5kZXYsICJpM2MgZG1hIHR4OjB4JXgsIGRtYSByeDow eCV4XG4iLCBkbV90eF9zdCwgZG1fcnhfc3QpOwo+ICsJCX0gZWxzZSBpZiAoKG1fc3RhdCAmIChN X1JYX0ZJRk9fV0FURVJNQVJLX0VOIHwgTV9SWF9GSUZPX0xBU1RfRU4pKSAmJgo+ICsJCQkgICAg IWdpM2MtPmN1cl9pc193cml0ZSAmJiBnaTNjLT5jdXJfYnVmKSB7Cj4gKwkJCS8qIEZJRk8gUlgg aGFuZGxpbmcgKi8KPiArCQkJdTMyIHJ4Y250ID0gcnhfc3QgJiBSWF9GSUZPX1dDX01TSzsKPiAr CQkJaW50IGF2YWlsID0gcnhjbnQgKiA0Owo+ICsJCQlpbnQgbmVlZCAgPSBnaTNjLT5jdXJfbGVu IC0gZ2kzYy0+Y3VyX2lkeDsKPiArCQkJaW50IG4gICAgID0gbWluKG5lZWQsIGF2YWlsKTsKPiAr Cj4gKwkJCWlmIChuID4gMCkgewo+ICsJCQkJaTNjX3JlYWRsX2ZpZm8oZ2kzYy0+c2UuYmFzZSAr IFNFX0dFTklfUlhfRklGT24sCj4gKwkJCQkJICAgICAgIGdpM2MtPmN1cl9idWYgKyBnaTNjLT5j dXJfaWR4LCBuKTsKPiArCQkJCWdpM2MtPmN1cl9pZHggKz0gbjsKPiArCQkJfQoKW1NldmVyaXR5 OiBIaWdoXQpXaGF0IGhhcHBlbnMgaW4gZ2VuaV9pM2NfaXJxKCkgd2hlbiBhbiBJM0MgdGFyZ2V0 IHJldHVybnMgYSB2YWxpZCBzaG9ydCByZWFkCnJlc3BvbnNlIChmb3IgZXhhbXBsZSwgYSAyLWJ5 dGUgcmVzcG9uc2UgdG8gYSA1LWJ5dGUgR0VUTVhEUyBvciAzLWJ5dGUgR0VUTVJMCkNDQyByZWFk KSBvciB0ZXJtaW5hdGVzIGEgcmVhZCBlYXJseSB2aWEgdGhlIFQtYml0PwoKRmlyc3QsIFJYX0ZJ Rk9fV0NfTVNLIGluIFNFX0dFTklfUlhfRklGT19TVEFUVVMgY291bnRzIDMyLWJpdCBGSUZPIHdv cmRzLCBhbmQKdmFsaWQgYnl0ZXMgaW4gdGhlIGZpbmFsIHBhcnRpYWwgd29yZCBhcmUgaW5kaWNh dGVkIGJ5IFJYX0xBU1QgYW5kClJYX0xBU1RfQllURV9WQUxJRF9NU0suIENvbXB1dGluZyBhdmFp bCA9IHJ4Y250ICogNCByb3VuZHMgYSAyLWJ5dGUgcmVzcG9uc2UKdXAgdG8gNCBieXRlcywgc28g Z2VuaV9pM2NfbWFzdGVyX3NlbmRfY2NjX2NtZCgpIHNldHMKY21kLT5kZXN0c1tpXS5wYXlsb2Fk LmFjdHVhbF9sZW4gPSBnaTNjLT5jdXJfaWR4IHRvIDQgKGZvciBHRVRNWERTLCBjYXVzaW5nCmkz Y19tYXN0ZXJfZ2V0bXhkc19sb2NrZWQoKSB0byBmYWlsIHdpdGggLUVJTykgb3IgMyAoZm9yIEdF VE1STCwgcmVhZGluZyBhCnBhZGRpbmcgYnl0ZSBhcyBtYXhfaWJpX2xlbikuCgpTZWNvbmQsIE1f R1BfSVJRXzBfRU4gKCJJM0Mgc2xhdmUgZWFybHkgcmVhZCB0ZXJtaW5hdGlvbiIpIGlzIGluY2x1 ZGVkIGluClNFX0kzQ19FUlIgYW5kIHNldHMgZ2kzYy0+ZXJyID0gLUVJTlZBTCBpbiBnZW5pX2kz Y19oYW5kbGVfZXJyKCkuIEJlY2F1c2UKdGhlIEZJRk8gUlggaGFuZGxlciBpcyBpbiBhbiBlbHNl LWlmIGJyYW5jaCBhZnRlciBpZiAobV9zdGF0ICYgU0VfSTNDX0VSUiAuLi4pLAphbiBlYXJseS10 ZXJtaW5hdGVkIHJlYWQgZmFpbHMgd2l0aCAtRUlOVkFMIGFuZCBsZWF2ZXMgdGhlIHJlY2VpdmVk IHdvcmRzCnVucmVhZCBpbiB0aGUgUlggRklGTy4KCj4gKwkJfSBlbHNlIGlmICgobV9zdGF0ICYg TV9UWF9GSUZPX1dBVEVSTUFSS19FTikgJiYKPiArCQkJICAgZ2kzYy0+Y3VyX2lzX3dyaXRlICYm IGdpM2MtPmN1cl9idWYpIHsKPiArCQkJLyogRklGTyBUWCBoYW5kbGluZyAqLwo+ICsJCQlpbnQg YXZhaWwgPSBnaTNjLT50eF93bSAqIDQ7Cj4gKwkJCWludCBuZWVkICA9IGdpM2MtPmN1cl9sZW4g LSBnaTNjLT5jdXJfaWR4Owo+ICsJCQlpbnQgbiAgICAgPSBtaW4obmVlZCwgYXZhaWwpOwo+ICsK PiArCQkJaWYgKG4gPiAwKSB7Cj4gKwkJCQlpM2Nfd3JpdGVsX2ZpZm8oZ2kzYy0+c2UuYmFzZSAr IFNFX0dFTklfVFhfRklGT24sCj4gKwkJCQkJCSh2b2lkICopKGdpM2MtPmN1cl9idWYgKyBnaTNj LT5jdXJfaWR4KSwgbik7Cj4gKwkJCQlnaTNjLT5jdXJfaWR4ICs9IG47Cj4gKwkJCX0KPiArCQl9 Cj4gKwo+ICsJCWlmICghZG1hX21vZGUgJiYgZ2kzYy0+Y3VyX2lkeCA9PSBnaTNjLT5jdXJfbGVu KQo+ICsJCQl3cml0ZWxfcmVsYXhlZCgwLCBnaTNjLT5zZS5iYXNlICsgU0VfR0VOSV9UWF9XQVRF Uk1BUktfUkVHKTsKPiArCX0KCltTZXZlcml0eTogSGlnaF0KQ2FuIE1fVFhfRklGT19XQVRFUk1B UktfRU4gY2F1c2UgYW4gdW5oYW5kbGVkIGludGVycnVwdCBzdG9ybSBpZiBnaTNjLT5jdXJfYnVm CmJlY29tZXMgTlVMTCB3aGlsZSBnaTNjLT5jdXJfaWR4IDwgZ2kzYy0+Y3VyX2xlbj8KCkluIF9p M2NfZ2VuaV9leGVjdXRlX2NvbW1hbmQoKToKCglnZW5pX3NlX3NldHVwX21fY21kKCZnaTNjLT5z ZSwgeGZlci0+bV9jbWQsIHhmZXItPm1fcGFyYW0pOwoJLi4uCglpZiAoeGZlci0+bW9kZSA9PSBH RU5JX1NFX0ZJRk8gJiYgbGVuID4gMCkgLyogR2V0IEZJRk8gSVJRICovCgkJd3JpdGVsX3JlbGF4 ZWQoMSwgZ2kzYy0+c2UuYmFzZSArIFNFX0dFTklfVFhfV0FURVJNQVJLX1JFRyk7CgpCZWNhdXNl IGdlbmlfc2Vfc2V0dXBfbV9jbWQoKSBpcyBjYWxsZWQgYmVmb3JlIGVuYWJsaW5nClNFX0dFTklf VFhfV0FURVJNQVJLX1JFRyB3aXRob3V0IGhvbGRpbmcgZ2kzYy0+aXJxX2xvY2ssIGFuIGltbWVk aWF0ZSBlcnJvcgpvciBhYm9ydCBpbnRlcnJ1cHQgY2FuIHJ1biBmaXJzdCBhbmQgY2xlYXIgU0Vf R0VOSV9UWF9XQVRFUk1BUktfUkVHLCBhZnRlcgp3aGljaCBfaTNjX2dlbmlfZXhlY3V0ZV9jb21t YW5kKCkgd3JpdGVzIDEgdG8gU0VfR0VOSV9UWF9XQVRFUk1BUktfUkVHIGFuZApzZXRzIGdpM2Mt PmN1cl9idWYgPSBOVUxMLiBMaWtld2lzZSwgb24gYSB0cmFuc2ZlciB0aW1lb3V0LApfaTNjX2dl bmlfZXhlY3V0ZV9jb21tYW5kKCkgc2V0cyBnaTNjLT5jdXJfYnVmID0gTlVMTCB3aXRob3V0IGNs ZWFyaW5nClNFX0dFTklfVFhfV0FURVJNQVJLX1JFRy4KCldoZW4gTV9UWF9GSUZPX1dBVEVSTUFS S19FTiB0aGVuIGZpcmVzIGluIGdlbmlfaTNjX2lycSgpIHdpdGgKZ2kzYy0+Y3VyX2J1ZiA9PSBO VUxMIGFuZCBnaTNjLT5jdXJfaWR4IDwgZ2kzYy0+Y3VyX2xlbiwgbmVpdGhlciB0aGUgVFgKYnJh bmNoIG5vciB0aGUgY3VyX2lkeCA9PSBjdXJfbGVuIGNoZWNrIGRpc2FibGVzIFNFX0dFTklfVFhf V0FURVJNQVJLX1JFRywKbGVhdmluZyB0aGUgbGV2ZWwtdHJpZ2dlcmVkIHdhdGVybWFyayBpbnRl cnJ1cHQgYXNzZXJ0ZWQgY29udGludW91c2x5LgoKPiArCj4gKwlpZiAobV9zdGF0KQo+ICsJCXdy aXRlbF9yZWxheGVkKG1fc3RhdCwgZ2kzYy0+c2UuYmFzZSArIFNFX0dFTklfTV9JUlFfQ0xFQVIp Owo+ICsKPiArCWlmIChkbWFfbW9kZSkgewo+ICsJCWlmIChkbV90eF9zdCkKPiArCQkJd3JpdGVs X3JlbGF4ZWQoZG1fdHhfc3QsIGdpM2MtPnNlLmJhc2UgKyBTRV9ETUFfVFhfSVJRX0NMUik7Cj4g KwkJaWYgKGRtX3J4X3N0KQo+ICsJCQl3cml0ZWxfcmVsYXhlZChkbV9yeF9zdCwgZ2kzYy0+c2Uu YmFzZSArIFNFX0RNQV9SWF9JUlFfQ0xSKTsKPiArCX0KPiArCj4gKwkvKiBpZiB0aGlzIGlzIGVy ciB3aXRoIGRvbmUtYml0IG5vdCBzZXQsIGhhbmRsZSB0aGF0IHRocm91Z2ggdGltZW91dC4gKi8K PiArCWlmIChtX3N0YXQgJiAoTV9DTURfRE9ORV9FTiB8IE1fQ01EX0FCT1JUX0VOKSkgewo+ICsJ CXdyaXRlbF9yZWxheGVkKDAsIGdpM2MtPnNlLmJhc2UgKyBTRV9HRU5JX1RYX1dBVEVSTUFSS19S RUcpOwo+ICsJCWNvbXBsZXRlKCZnaTNjLT5kb25lKTsKPiArCX0gZWxzZSBpZiAoKGRtX3R4X3N0 ICYgVFhfRE1BX0RPTkUpIHx8IChkbV9yeF9zdCAmIChSWF9ETUFfRE9ORSB8IFJYX1JFU0VUX0RP TkUpKSkgewo+ICsJCWNvbXBsZXRlKCZnaTNjLT5kb25lKTsKPiArCX0KPiArCj4gKwlyZXR1cm4g SVJRX0hBTkRMRUQ7Cj4gK30KWyAuLi4gXQo+ICtzdGF0aWMgaW50IF9pM2NfZ2VuaV9leGVjdXRl X2NvbW1hbmQoc3RydWN0IGdlbmlfaTNjX2RldiAqZ2kzYywgc3RydWN0IGdlbmlfaTNjX3hmZXJf cGFyYW1zICp4ZmVyKQo+ICt7ClsgLi4uIF0KPiArCWlmICh4ZmVyLT5tb2RlID09IEdFTklfU0Vf RE1BKSB7Cj4gKwkJaWYgKGdpM2MtPmVycikgewo+ICsJCQlpZiAoaXNfd3JpdGUpCj4gKwkJCQl3 cml0ZWxfcmVsYXhlZCgxLCBnaTNjLT5zZS5iYXNlICsgU0VfRE1BX1RYX0ZTTV9SU1QpOwo+ICsJ CQllbHNlCj4gKwkJCQl3cml0ZWxfcmVsYXhlZCgxLCBnaTNjLT5zZS5iYXNlICsgU0VfRE1BX1JY X0ZTTV9SU1QpOwo+ICsKPiArCQkJdGltZV9yZW1haW5pbmcgPSB3YWl0X2Zvcl9jb21wbGV0aW9u X3RpbWVvdXQoJmdpM2MtPmRvbmUsIFhGRVJfVElNRU9VVCk7Cj4gKwkJCWRldl9kYmcoZ2kzYy0+ c2UuZGV2LCAiVGltZW91dCBjb21wbGV0aW5nIERNQSB0cmFuc2ZlclxuIik7Cj4gKwkJfQo+ICsK PiArCQlpZiAoaXNfd3JpdGUpCj4gKwkJCWdlbmlfc2VfdHhfZG1hX3VucHJlcCgmZ2kzYy0+c2Us IHR4X2RtYSwgbGVuKTsKPiArCQllbHNlCj4gKwkJCWdlbmlfc2VfcnhfZG1hX3VucHJlcCgmZ2kz Yy0+c2UsIHJ4X2RtYSwgbGVuKTsKPiArCX0KCltTZXZlcml0eTogSGlnaF0KSW4gX2kzY19nZW5p X2V4ZWN1dGVfY29tbWFuZCgpIGFuZCBnZW5pX2kzY19pcnEoKSwgaG93IGlzIGdpM2MtPmRvbmUK c3luY2hyb25pemVkIGFjcm9zcyBtdWx0aS1jb21tYW5kIGxvb3BzIGFuZCBETUEgRlNNIHJlc2V0 cz8KCjEuIENhbGxlcnMgb25seSBjYWxsIHJlaW5pdF9jb21wbGV0aW9uKCZnaTNjLT5kb25lKSBv bmNlIGJlZm9yZSB0aGVpcgogICB0cmFuc2ZlciBsb29wcyByYXRoZXIgdGhhbiBpbiBfaTNjX2dl bmlfZXhlY3V0ZV9jb21tYW5kKCkgYmVmb3JlIGVhY2gKICAgY29tbWFuZCBhbmQgYmVmb3JlIHdh aXRpbmcgb24gU0VfRE1BX1RYX0ZTTV9SU1QgLyBTRV9ETUFfUlhfRlNNX1JTVC4KMi4gSW4gZ2Vu aV9pM2NfaXJxKCksIHRoZSBETUEgY29tcGxldGlvbiBjaGVjayBoYW5kbGVzIFJYX1JFU0VUX0RP TkUgaW4KICAgZG1fcnhfc3QsIGJ1dCBvbWl0cyBUWF9SRVNFVF9ET05FIGluIGRtX3R4X3N0LCBz byB3YWl0aW5nIGZvcgogICBTRV9ETUFfVFhfRlNNX1JTVCBpbiBfaTNjX2dlbmlfZXhlY3V0ZV9j b21tYW5kKCkgd2lsbCBhbHdheXMgdGltZSBvdXQKICAgYmVmb3JlIGdlbmlfc2VfdHhfZG1hX3Vu cHJlcCgpIHVubWFwcyB0aGUgYnVmZmVyLgozLiBCZWNhdXNlIG1fc3RhdCBpcyBub3QgbWFza2Vk IHdpdGggU0VfR0VOSV9NX0lSUV9FTiwgaWYgTV9DTURfRE9ORV9FTiBpcwogICBzZXQgaW4gbV9z dGF0IHdoaWxlIGRtYV9tb2RlIGlzIGFjdGl2ZSwgZ2VuaV9pM2NfaXJxKCkgY2FuIGNvbXBsZXRl CiAgIGdpM2MtPmRvbmUgYmVmb3JlIFRYX0RNQV9ET05FIG9yIFJYX0RNQV9ET05FIGZpcmVzLCBj YXVzaW5nCiAgIF9pM2NfZ2VuaV9leGVjdXRlX2NvbW1hbmQoKSB0byB1bm1hcCB0aGUgRE1BIGJ1 ZmZlciB3aGlsZSBETUEgaXMgc3RpbGwgaW4KICAgZmxpZ2h0IGFuZCBsZWF2aW5nIGFuIGV4dHJh IGNvbXBsZXRpb24gaW4gZ2kzYy0+ZG9uZSBmb3IgdGhlIG5leHQgY29tbWFuZC4KClsgLi4uIF0K PiArc3RhdGljIGludCBnZW5pX2kzY19tYXN0ZXJfcHJpdl94ZmVycyhzdHJ1Y3QgaTNjX2Rldl9k ZXNjICpkZXYsIHN0cnVjdCBpM2NfeGZlciAqeGZlcnMsCj4gKwkJCQkgICAgICBpbnQgbnhmZXJz LCBlbnVtIGkzY194ZmVyX21vZGUgbW9kZSkKPiArewo+ICsJc3RydWN0IGkzY19tYXN0ZXJfY29u dHJvbGxlciAqbSA9IGkzY19kZXZfZ2V0X21hc3RlcihkZXYpOwo+ICsJc3RydWN0IGdlbmlfaTNj X2RldiAqZ2kzYyA9IHRvX2dlbmlfaTNjX21hc3RlcihtKTsKPiArCWJvb2wgdXNlXzdlID0gZmFs c2U7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCXNjb3BlZF9ndWFyZChtdXRleCwgJmdpM2MtPmxvY2sp IHsKWyAuLi4gXQo+ICsJCXFjb21fZ2VuaV9pM2NfY29uZihnaTNjLCBQVVNIX1BVTExfTU9ERSk7 Cj4gKwo+ICsJCWZvciAoaW50IGkgPSAwOyBpIDwgbnhmZXJzOyBpKyspIHsKPiArCQkJYm9vbCBz dGFsbCA9IChpIDwgKG54ZmVycyAtIDEpKTsKPiArCQkJc3RydWN0IGdlbmlfaTNjX3hmZXJfcGFy YW1zIHhmZXIgPSB7IEdFTklfU0VfRklGTyB9Owo+ICsKPiArCQkJeGZlci5tX3BhcmFtICA9IChz dGFsbCA/IFNUT1BfU1RSRVRDSCA6IDApOwo+ICsJCQl4ZmVyLm1fcGFyYW0gfD0gRklFTERfUFJF UChTTEFWRV9BRERSX01BU0ssIGRldi0+aW5mby5keW5fYWRkcik7Cj4gKwkJCXhmZXIubV9wYXJh bSB8PSAodXNlXzdlKSA/IFVTRV83RSA6IDA7Cj4gKwo+ICsJCQkvKiB1c2VfN2UgPSB0cnVlIG9u bHkgZm9yIGxhc3QgdHJhbnNmZXIgKi8KPiArCQkJdXNlXzdlID0gKGkgPT0gbnhmZXJzIC0gMSk7 CgpbU2V2ZXJpdHk6IEhpZ2hdCkluIGdlbmlfaTNjX21hc3Rlcl9wcml2X3hmZXJzKCksIHVzZV83 ZSBpcyBpbml0aWFsaXplZCB0byBmYWxzZSBhbmQgb25seSBzZXQKdG8gKGkgPT0gbnhmZXJzIC0g MSkgYWZ0ZXIgeGZlci5tX3BhcmFtIHw9ICh1c2VfN2UpID8gVVNFXzdFIDogMCBoYXMgYWxyZWFk eQpiZWVuIGV2YWx1YXRlZC4KCk9uIGl0ZXJhdGlvbnMgaSA8IG54ZmVycyAtIDEsIHVzZV83ZSBp cyBmYWxzZTsgb24gdGhlIGZpbmFsIGl0ZXJhdGlvbgppID09IG54ZmVycyAtIDEsIHVzZV83ZSBp cyBzdGlsbCBmYWxzZSB3aGVuIHhmZXIubV9wYXJhbSBpcyBidWlsdCBhbmQgb25seQpiZWNvbWVz IHRydWUgcmlnaHQgYmVmb3JlIHRoZSBsb29wIGV4aXRzLiBBcyBhIHJlc3VsdCwgVVNFXzdFIGlz IG5ldmVyIHNldCBvbgphbnkgdHJhbnNmZXIgKGFuZCBzaG91bGRuJ3QgVVNFXzdFIGJlIHNldCBv biB0aGUgZmlyc3QgdHJhbnNmZXIgaSA9PSAwLCBhcyBpbgpnZW5pX2kzY19tYXN0ZXJfc2VuZF9j Y2NfY21kKCkgYW5kIGdlbmlfaTNjX3BlcmZvcm1fZGFhKCk/KS4KCj4gKwo+ICsJCQlpZiAoeGZl cnNbaV0ucm53KSB7ClsgLi4uIF0KPiArc3RhdGljIGludCBnZW5pX2kzY19tYXN0ZXJfaTJjX3hm ZXJzKHN0cnVjdCBpMmNfZGV2X2Rlc2MgKmRldiwgc3RydWN0IGkyY19tc2cgKm1zZ3MsIGludCBu dW0pCj4gK3sKWyAuLi4gXQo+ICsJZm9yIChpbnQgaSA9IDA7IGkgPCBudW07IGkrKykgewo+ICsJ CXN0cnVjdCBnZW5pX2kzY194ZmVyX3BhcmFtcyB4ZmVyOwo+ICsKPiArCQl4ZmVyLm1fY21kICAg ID0gKG1zZ3NbaV0uZmxhZ3MgJiBJMkNfTV9SRCkgPyBJMkNfUkVBRCA6IEkyQ19XUklURTsKPiAr CQl4ZmVyLm1fcGFyYW0gID0gKGkgPCAobnVtIC0gMSkpID8gU1RPUF9TVFJFVENIIDogMDsKPiAr CQl4ZmVyLm1fcGFyYW0gfD0gRklFTERfUFJFUChTTEFWRV9BRERSX01BU0ssIG1zZ3NbaV0uYWRk cik7Cj4gKwkJeGZlci5tb2RlICAgICA9IG1zZ3NbaV0ubGVuID4gKGdpM2MtPnR4X2RlcHRoIC8g MikgPwo+ICsJCQkJR0VOSV9TRV9ETUEgOiBHRU5JX1NFX0ZJRk87Cj4gKwkJaWYgKG1zZ3NbaV0u ZmxhZ3MgJiBJMkNfTV9SRCkKPiArCQkJcmV0ID0gaTNjX2dlbmlfZXhlY3V0ZV9yZWFkX2NvbW1h bmQoZ2kzYywgJnhmZXIsIG1zZ3NbaV0uYnVmLAo+ICsJCQkJCQkJICAgIG1zZ3NbaV0ubGVuKTsK PiArCQllbHNlCj4gKwkJCXJldCA9IGkzY19nZW5pX2V4ZWN1dGVfd3JpdGVfY29tbWFuZChnaTNj LCAmeGZlciwgbXNnc1tpXS5idWYsCj4gKwkJCQkJCQkgICAgIG1zZ3NbaV0ubGVuKTsKPiArCQlp ZiAocmV0KQo+ICsJCQlicmVhazsKPiArCX0KCltTZXZlcml0eTogSGlnaF0KSW4gZ2VuaV9pM2Nf bWFzdGVyX2kyY194ZmVycygpLCB3aGVuIG1zZ3NbaV0ubGVuID4gKGdpM2MtPnR4X2RlcHRoIC8g MiksCm1zZ3NbaV0uYnVmIGlzIHBhc3NlZCBkaXJlY3RseSB0byBHRU5JX1NFX0RNQSBhbmQgbWFw cGVkIHdpdGgKZG1hX21hcF9zaW5nbGUoKSBpbiBnZW5pX3NlX3R4X2RtYV9wcmVwKCkgLyBnZW5p X3NlX3J4X2RtYV9wcmVwKCkuCgpTaW5jZSBpMmNfbXNnIGJ1ZmZlcnMgYXJlIG5vdCBndWFyYW50 ZWVkIHRvIGJlIERNQS1zYWZlIChhcyBub3RlZCBpbiB0aGUKc3RydWN0IGkzY19tYXN0ZXJfY29u dHJvbGxlcl9vcHMgZG9jdW1lbnRhdGlvbiBpbiBpbmNsdWRlL2xpbnV4L2kzYy9tYXN0ZXIuaCks CnNob3VsZCB0aGlzIHVzZSBpMmNfZ2V0X2RtYV9zYWZlX21zZ19idWYoKSBhbmQgaTJjX3B1dF9k bWFfc2FmZV9tc2dfYnVmKCk/CgpBbHNvLCBmb3IgR0VOSV9TRV9ETUEgdHJhbnNmZXJzOgotIElu IF9pM2NfZ2VuaV9leGVjdXRlX2NvbW1hbmQoKSwgZ2VuaV9zZV9zZXR1cF9tX2NtZCgpIHN0YXJ0 cyB0aGUgaGFyZHdhcmUKICBjb21tYW5kIGJlZm9yZSBnZW5pX3NlX3R4X2RtYV9wcmVwKCkgb3Ig Z2VuaV9zZV9yeF9kbWFfcHJlcCgpIHNldHMgdXAgdGhlCiAgRE1BIHRyYW5zZmVyIChvciBmYWxs cyBiYWNrIHRvIEdFTklfU0VfRklGTykuCi0gSW4gaTNjX2dlbmlfcmVzb3VyY2VzX2luaXQoKSwg YXZnX2J3IGlzIHNldCBvbiBHRU5JX1RPX0NPUkUgYW5kCiAgQ1BVX1RPX0dFTkksIGJ1dCBnaTNj LT5zZS5pY2NfcGF0aHNbR0VOSV9UT19ERFJdLmF2Z19idyBpcyBsZWZ0IGF0IDAuCgpbIC4uLiBd Cj4gK3N0YXRpYyBpbnQgZ2VuaV9pM2NfaHdfaW5pdChzdHJ1Y3QgZ2VuaV9pM2NfZGV2ICpnaTNj LCBzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ICt7Cj4gKwl1MzIgcHJvdG8sIGZpZm9f ZGlzYWJsZTsKPiArCj4gKwlwcm90byA9IGdlbmlfc2VfcmVhZF9wcm90bygmZ2kzYy0+c2UpOwo+ ICsJaWYgKHByb3RvICE9IEdFTklfU0VfSTNDKSB7Cj4gKwkJZ2VuaV9zZV9yZXNvdXJjZXNfb2Zm KCZnaTNjLT5zZSk7Cj4gKwkJcmV0dXJuIGRldl9lcnJfcHJvYmUoZ2kzYy0+c2UuZGV2LCAtRU5Y SU8sICJJbnZhbGlkIHByb3RvICVkXG4iLCBwcm90byk7Cj4gKwl9Cj4gKwo+ICsJZmlmb19kaXNh YmxlID0gcmVhZGxfcmVsYXhlZChnaTNjLT5zZS5iYXNlICsgR0VOSV9JRl9ESVNBQkxFX1JPKTsK PiArCWlmIChmaWZvX2Rpc2FibGUpIHsKPiArCQlnZW5pX3NlX3Jlc291cmNlc19vZmYoJmdpM2Mt PnNlKTsKPiArCQlyZXR1cm4gZGV2X2Vycl9wcm9iZShnaTNjLT5zZS5kZXYsIC1FTlhJTywgIkdQ SSBETUEgbW9kZSBub3Qgc3VwcG9ydGVkXG4iKTsKPiArCX0KWyAuLi4gXQo+ICtzdGF0aWMgaW50 IGdlbmlfaTNjX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gK3sKWyAuLi4g XQo+ICsJcmV0ID0gZ2VuaV9zZV9yZXNvdXJjZXNfb24oJmdpM2MtPnNlKTsKPiArCWlmIChyZXQp Cj4gKwkJcmV0dXJuIGRldl9lcnJfcHJvYmUoJnBkZXYtPmRldiwgcmV0LCAiRXJyb3IgdHVybmlu ZyByZXNvdXJjZXMgT05cbiIpOwo+ICsKPiArCXJldCA9IGdlbmlfaTNjX2h3X2luaXQoZ2kzYywg cGRldik7Cj4gKwlnZW5pX3NlX3Jlc291cmNlc19vZmYoJmdpM2MtPnNlKTsKPiArCWlmIChyZXQp Cj4gKwkJcmV0dXJuIHJldDsKWyAuLi4gXQo+ICtzdGF0aWMgaW50IGdlbmlfaTNjX3J1bnRpbWVf c3VzcGVuZChzdHJ1Y3QgZGV2aWNlICpkZXYpCj4gK3sKPiArCXN0cnVjdCBnZW5pX2kzY19kZXYg KmdpM2MgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsKPiArCj4gKwlkaXNhYmxlX2lycShnaTNjLT5p cnEpOwo+ICsJZ2VuaV9zZV9yZXNvdXJjZXNfb2ZmKCZnaTNjLT5zZSk7Cj4gKwo+ICsJcmV0dXJu IDA7Cj4gK30KCltTZXZlcml0eTogTWVkaXVtXQpJZiBnZW5pX2kzY19od19pbml0KCkgZmFpbHMs IGl0IGNhbGxzIGdlbmlfc2VfcmVzb3VyY2VzX29mZigmZ2kzYy0+c2UpIGJlZm9yZQpyZXR1cm5p bmcsIGFuZCB0aGVuIGdlbmlfaTNjX3Byb2JlKCkgY2FsbHMgZ2VuaV9zZV9yZXNvdXJjZXNfb2Zm KCZnaTNjLT5zZSkgYQpzZWNvbmQgdGltZS4gV29uJ3QgdGhpcyB1bmRlcmZsb3cgdGhlIGVuYWJs ZS9wcmVwYXJlIGNvdW50cyBvbiBzZS0+Y2xrIGFuZAp0aGUgc2hhcmVkIFFVUCB3cmFwcGVyIGNs b2Nrcz8KCkFsc28sIGluIGdlbmlfaTNjX3J1bnRpbWVfc3VzcGVuZCgpLCBpZiBnZW5pX3NlX3Jl c291cmNlc19vZmYoJmdpM2MtPnNlKQpmYWlscyAoZm9yIGluc3RhbmNlIGlmIHBpbmN0cmxfcG1f c2VsZWN0X3NsZWVwX3N0YXRlKCkgcmV0dXJucyBhbiBlcnJvcgpiZWZvcmUgY2xvY2tzIGFyZSBk aXNhYmxlZCksIHNob3VsZCB0aGUgZXJyb3IgYmUgcHJvcGFnYXRlZCBhZnRlciByZS1lbmFibGlu ZwpnaTNjLT5pcnE/CgotLSAKU2FzaGlrbyBBSSByZXZpZXcgwrcgaHR0cHM6Ly9zYXNoaWtvLmRl di8jL3BhdGNoc2V0LzIwMjYxMTA0MTExNjEwLjM3MzkwOTUtMS1tdWtlc2guc2F2YWxpeWFAb3Nz LnF1YWxjb21tLmNvbT9wYXJ0PTIKCi0tIApsaW51eC1pM2MgbWFpbGluZyBsaXN0CmxpbnV4LWkz Y0BsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4v bGlzdGluZm8vbGludXgtaTNjCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793792633; b=UsJU3exRLrWZeUCFz4CkqbMED1ZM9PSuQVXI9e/p+oNDGkMPvY3UjxvI6NdZw89WbTqi SySGBwCl12YDsIE3KAsTQECJSAp3LfzRHcGaEVjO4zDLusjwNHrBP5y2rOVMjUXDC+NSP VRTegdsRs9ckZnuX//53PZ+48+JoPl/z7qU85KNtzGP6FIFMBPNC+qUhxpnnXl+BiVGQ7 PM+B3WS3JQOvHhXDyYf1D0hknI8U1yizHBxZSzuituUNkEkJWBgNh0oXO8NNhUcmn2q4C sAcnYtGKRa+56dPfJeqTiMTnykMyNAbuk77e1XAWh418XZ/0RuuwmBgXgXl0pcwffGA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793792633; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=CS23nMGiYphLe/0ej6egsSAB2f8i8m7h8S/Y9UHFc0I=; b=J50ubVWL8PsWJFQLPRX7HWkOZvVeRaR8ekjd4EiRsGLibuyYdngP0wMT9qdXxmsv2Nej 2zoXNUDuiAMCwkq4PGH8NkeElh3qEaO/UgcT7NWJ8qGrYkQUgm0kP8ufELvB7zVzuu5eY IUqTSitGgqI0D73XlFw4g0mqD4kHipEz4lRCq3W1mWZ0HeUX8ADov8yEObRZG9ADMoL2K 2BSdxDc31DEhewIRiT6Czlu1FwsIjU/SLXZtYITDy2PalcLlHyTws9+hHzdOqAQNoHR3q FsNim96fnkFNEZqsYLgr3KXgHHFbGwfSIqzS0wYkDl/wrhhgjc+uJu/XxB03uS/LM1g== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=AlG3bo64; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BBFA606A338 for ; Wed, 4 Nov 2026 11:43:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=AlG3bo64 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 440591F000C1; Wed, 4 Nov 2026 11:43:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793792632; bh=CS23nMGiYphLe/0ej6egsSAB2f8i8m7h8S/Y9UHFc0I=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=AlG3bo64TkwY/7W+PxQLU6vpw6d4VdFu2xw5IUNg/tN6csdAQSB17w/v+lDRmwsR3 hrpwp+2uO0dyQolroXYKA9CeDn6IuR9txmVDg3Cs7jjPAb3O/ARzraPlgGVSD6YKt8 zYKp3OjrWaTfKdNK01tIA02AiefN4wf2PuSN2SSvjkpZEjn8/YozuO0p58OOwUkEBX JHz0xcZ0ng0ztB8PJNpX/66Zg/R+StH4JIFM5FxQsmvpDVMK1B8yq4eaPeKbcf/kSW smNAtM7lFUkqV6DnClqz6ZcftiAhQTNAQUW0IYWq7YRX3YdjwRrWXkzbClgA2amNUm bu0H2itBNPgxA== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v7 2/3] i3c: master: Add Qualcomm I3C controller driver Reply-To: sashiko-reviews@lists.linux.dev To: "Mukesh Kumar Savaliya" , linux-i3c@lists.infradead.org, devicetree@vger.kernel.org Cc: robh@kernel.org, conor+dt@kernel.org, Frank.Li@kernel.org, "Alexandre Belloni" In-Reply-To: <20261104111610.3739095-2-mukesh.savaliya@oss.qualcomm.com> References: <20261104111610.3739095-1-mukesh.savaliya@oss.qualcomm.com> <20261104111610.3739095-2-mukesh.savaliya@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Wed, 04 Nov 2026 11:43:51 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 10 potential issue= (s) to consider: - [High] i3c: qcom-geni: use_7e updated after m_param in geni_i3c_master_pr= iv_xfers() - [High] i3c: qcom-geni: broken I3C_ADDR_MASK and DAA handling in geni_i3c_= perform_daa() - [High] i3c: qcom-geni: invalid clock lookup and 1 MHz cycle count in geni= _i3c_clk_map - [High] i3c: qcom-geni: unsafe I2C DMA mapping and broken DMA reset handli= ng - [High] i3c: qcom-geni: broken short RX FIFO reads and early termination i= n geni_i3c_irq() - [High] i3c: qcom-geni: NACK error overwrite and status bitmask mismatch i= n geni_i3c_handle_err() - [High] i3c: qcom-geni: missing reinit_completion() and TX_RESET_DONE in _= i3c_geni_execute_command() - [High] i3c: qcom-geni: TX watermark race and unhandled IRQ storm in geni_= i3c_irq() - [Medium] i3c: qcom-geni: double geni_se_resources_off() call in geni_i3c_= probe() - [Low] i3c: qcom-geni: unused variable m_stat_mask in geni_i3c_irq() -- commit 2ad15e60246cd7898205f431d98abb7e053d2d97 Author: Mukesh Kumar Savaliya i3c: master: Add Qualcomm I3C controller driver This commit adds a driver for the Qualcomm QUPv3 GENI-based I3C master controller supporting I3C SDR and legacy I2C transfers. > diff --git a/drivers/i3c/master/i3c-qcom-geni.c b/drivers/i3c/master/i3c-= qcom-geni.c > new file mode 100644 > index 0000000000000..2fee77e681e26 > --- /dev/null > +++ b/drivers/i3c/master/i3c-qcom-geni.c [ ... ] > +#define I3C_AUTO_SUSPEND_DELAY 250 > +#define PACKING_BYTES_PER_WORD 4 > +#define XFER_TIMEOUT 250 > + > +#define I3C_ADDR_MASK (I2C_MAX_ADDR >> 1) [ ... ] > +struct geni_i3c_dev { [ ... ] > + u8 *cur_buf; > + u8 last_addr; > + bool cur_is_write; > + int cur_len; > + int cur_idx; > + DECLARE_BITMAP(newaddrslots, 64); > + > + const struct geni_i3c_clk_settings *clk_cfg; > + const struct geni_i3c_clk_settings *clk_od_cfg; > +}; [Severity: High] Since I2C_MAX_ADDR is defined as GENMASK(6, 0) (0x7f) in include/linux/i3c/master.h, shifting it right by 1 makes I3C_ADDR_MASK 0x3f (6 bits instead of 7 bits), and newaddrslots is only 64 bits wide instead of I3C_MAX_ADDR + 1 (128). Later in geni_i3c_perform_daa(): addr =3D i3c_master_get_free_addr(&gi3c->ctrlr, gi3c->last_addr + 1); if (addr > I3C_ADDR_MASK) return -EINVAL; gi3c->last_addr =3D addr; set_bit(addr, gi3c->newaddrslots); ... ret =3D i3c_geni_execute_write_command(gi3c, &xfer, tx_buf, 1); if (ret) break; Doesn't this reject valid 7-bit dynamic addresses from 0x40 to 0x7d (as well as truncating negative error codes from i3c_master_get_free_addr() into u8)? Also, in geni_i3c_perform_daa() and geni_i3c_master_send_ccc_cmd(): - gi3c->last_addr is never reset between DAA runs, so repeated DAA invocations will only search above the previous address until the range is exhausted. - set_bit(addr, gi3c->newaddrslots) is called before i3c_geni_execute_write_command() sends the dynamic address to the target. If that write fails, geni_i3c_perform_daa() breaks out and returns 0 with addr still set in newaddrslots, causing geni_i3c_master_do_daa() to call i3c_master_add_i3c_dev_locked() for an unassigned address. - geni_i3c_master_send_ccc_cmd() ignores the return value of geni_i3c_perform_daa(gi3c). Should I3C_ADDR_MASK be I3C_MAX_ADDR (0x7f) with newaddrslots sized to I3C_MAX_ADDR + 1, and should set_bit(addr, gi3c->newaddrslots) happen only after the address write succeeds? [ ... ] > +static const struct geni_i3c_clk_settings geni_i3c_clk_map[] =3D { > + { > + .clk_freq_out =3D 100 * HZ_PER_KHZ, > + .clk_src_freq =3D 19200 * HZ_PER_KHZ, > + .clk_div =3D 1, > + .i2c_t_high_cnt =3D 76, > + .i2c_t_low_cnt =3D 90, > + .i3c_t_high_cnt =3D 7, > + .i3c_t_cycle_cnt =3D 8, > + .i2c_t_cycle_cnt =3D 192, > + }, > + { > + .clk_freq_out =3D 400 * HZ_PER_KHZ, > + .clk_src_freq =3D 19200 * HZ_PER_KHZ, > + .clk_div =3D 1, > + .i2c_t_high_cnt =3D 12, > + .i2c_t_low_cnt =3D 24, > + .i3c_t_high_cnt =3D 7, > + .i3c_t_cycle_cnt =3D 8, > + .i2c_t_cycle_cnt =3D 48 > + }, > + { > + .clk_freq_out =3D 1000 * HZ_PER_KHZ, > + .clk_src_freq =3D 19200 * HZ_PER_KHZ, > + .clk_div =3D 1, > + .i2c_t_high_cnt =3D 4, > + .i2c_t_low_cnt =3D 9, > + .i3c_t_high_cnt =3D 7, > + .i3c_t_cycle_cnt =3D 0, > + .i2c_t_cycle_cnt =3D 19 > + }, > + { > + .clk_freq_out =3D 12500 * HZ_PER_KHZ, > + .clk_src_freq =3D 100000 * HZ_PER_KHZ, > + .clk_div =3D 1, > + .i2c_t_high_cnt =3D 45, > + .i2c_t_low_cnt =3D 63, > + .i3c_t_high_cnt =3D 6, > + .i3c_t_cycle_cnt =3D 7, > + .i2c_t_cycle_cnt =3D 110 > + } > +}; > + > +static int geni_i3c_clk_map_idx(struct geni_i3c_dev *gi3c) > +{ > + const struct geni_i3c_clk_settings *clk_table_idx =3D geni_i3c_clk_map; > + struct i3c_master_controller *m =3D &gi3c->ctrlr; > + struct i3c_bus *bus =3D i3c_master_get_bus(m); > + > + for (int i =3D 0; i < ARRAY_SIZE(geni_i3c_clk_map); i++, clk_table_idx+= +) { > + if (clk_table_idx->clk_freq_out =3D=3D bus->scl_rate.i3c && > + clk_table_idx->clk_src_freq =3D=3D gi3c->clk_src_freq) > + gi3c->clk_cfg =3D clk_table_idx; > + > + if (clk_table_idx->clk_freq_out =3D=3D bus->scl_rate.i2c) > + gi3c->clk_od_cfg =3D clk_table_idx; > + } > + > + if (!gi3c->clk_cfg || !gi3c->clk_od_cfg) > + return -EINVAL; > + > + return 0; > +} [Severity: High] How does geni_i3c_clk_map_idx() behave on a pure I3C bus or a mixed-slow bus? In i3c_bus_set_mode(), when bus->mode is I3C_BUS_MODE_PURE and no i2c-scl-hz property is set in devicetree, bus->scl_rate.i2c remains 0. Because no entry in geni_i3c_clk_map[] has clk_freq_out =3D=3D 0, gi3c->clk_od_cfg stays NUL= L and geni_i3c_master_bus_init() fails with -EINVAL. Conversely, in I3C_BUS_MODE_MIXED_SLOW (where i3c_bus_set_mode() clamps bus->scl_rate.i3c to bus->scl_rate.i2c), i3c_geni_resources_init() hardcodes gi3c->clk_src_freq to 100 MHz while the 100 kHz, 400 kHz, and 1000 kHz entries in geni_i3c_clk_map[] all have clk_src_freq set to 19.2 MHz, so gi3c->clk_cfg stays NULL and geni_i3c_clk_map_idx() also returns -EINVAL. Also, in the 1000 kHz entry of geni_i3c_clk_map[], i3c_t_cycle_cnt is 0 whi= le i3c_t_high_cnt is 7 (whereas the 100 kHz and 400 kHz entries use i3c_t_cycle_cnt =3D 8). Is programming SE_I3C_SCL_CYCLE to 0 when qcom_geni_i3c_conf(gi3c, OPEN_DRAIN_MODE) selects the 1000 kHz entry intentional? [ ... ] > +static void geni_i3c_handle_err(struct geni_i3c_dev *gi3c, u32 status) > +{ > + dev_dbg(gi3c->se.dev, "len:%d, %s\n", > + gi3c->cur_len, gi3c->cur_is_write ? "write" : "read"); > + > + if (status & M_GP_IRQ_0_EN) { > + gi3c->err =3D -EINVAL; > + dev_dbg(gi3c->se.dev, "I3C slave early read termination\n"); > + } [ ... ] > + if (status & M_CMD_ABORT_EN) { > + gi3c->err =3D -ETIMEDOUT; > + dev_dbg(gi3c->se.dev, "Abort after timeout successful\n"); > + } > + > + if (status =3D=3D GENI_TIMEOUT) { > + gi3c->err =3D -ETIMEDOUT; > + dev_dbg(gi3c->se.dev, "I3C transaction timed out\n"); > + } > +} [Severity: High] Won't geni_i3c_handle_err() clobber an earlier NACK error (-ENOTCONN or -EBUSY) with -ETIMEDOUT when a transfer times out and aborts? When a NACK interrupt fires without M_CMD_DONE_EN set, geni_i3c_irq() recor= ds -ENOTCONN or -EBUSY in gi3c->err and waits for the timeout path in _i3c_geni_execute_command() to abort the command. Both the timeout path (passing GENI_TIMEOUT) and the subsequent M_CMD_ABORT_EN interrupt overwrite gi3c->err with -ETIMEDOUT, so geni_i3c_master_send_ccc_cmd() no longer sees -ENOTCONN or -EBUSY and cannot set cmd->err =3D I3C_ERROR_M2. In addition, status in geni_i3c_handle_err() is checked both as an SE_GENI_M_IRQ_STATUS bitmask and for equality with the enum constant GENI_TIMEOUT (which has value 9, or M_CMD_FAILURE_EN | M_CMD_DONE_EN). And if geni_i3c_irq() enters the error branch due to dm_rx_st & DM_I3C_CB_ERR or M_CMD_FAILURE_EN alone, geni_i3c_handle_err(gi3c, m_stat) leaves gi3c->err = as 0. Should gi3c->err only be updated when it is not already set, with a fallback error code when none of the specific M_GP_IRQ_* bits match? > + > +static irqreturn_t geni_i3c_irq(int irq, void *dev) > +{ > + struct geni_i3c_dev *gi3c =3D dev; > + u32 m_stat_mask, dm_tx_st, dm_rx_st; > + u32 m_stat, rx_st, dma_mode; > + > + m_stat =3D readl_relaxed(gi3c->se.base + SE_GENI_M_IRQ_STATUS); > + m_stat_mask =3D readl_relaxed(gi3c->se.base + SE_GENI_M_IRQ_EN); [Severity: Low] In geni_i3c_irq(), m_stat_mask is assigned here but never used, which will trigger an unused-but-set-variable compiler warning. Should m_stat be masked with m_stat_mask, or should m_stat_mask be removed? > + rx_st =3D readl_relaxed(gi3c->se.base + SE_GENI_RX_FIFO_STATUS); > + dm_tx_st =3D readl_relaxed(gi3c->se.base + SE_DMA_TX_IRQ_STAT); > + dm_rx_st =3D readl_relaxed(gi3c->se.base + SE_DMA_RX_IRQ_STAT); > + dma_mode =3D readl_relaxed(gi3c->se.base + SE_GENI_DMA_MODE_EN); > + > + scoped_guard(spinlock, &gi3c->irq_lock) { > + if (m_stat & SE_I3C_ERR || dm_rx_st & DM_I3C_CB_ERR) { > + geni_i3c_handle_err(gi3c, m_stat); > + /* Disable the TX Watermark interrupt to stop TX */ > + if (!dma_mode) > + writel_relaxed(0, gi3c->se.base + SE_GENI_TX_WATERMARK_REG); > + } else if (dma_mode) { > + dev_dbg(gi3c->se.dev, "i3c dma tx:0x%x, dma rx:0x%x\n", dm_tx_st, dm_= rx_st); > + } else if ((m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) && > + !gi3c->cur_is_write && gi3c->cur_buf) { > + /* FIFO RX handling */ > + u32 rxcnt =3D rx_st & RX_FIFO_WC_MSK; > + int avail =3D rxcnt * 4; > + int need =3D gi3c->cur_len - gi3c->cur_idx; > + int n =3D min(need, avail); > + > + if (n > 0) { > + i3c_readl_fifo(gi3c->se.base + SE_GENI_RX_FIFOn, > + gi3c->cur_buf + gi3c->cur_idx, n); > + gi3c->cur_idx +=3D n; > + } [Severity: High] What happens in geni_i3c_irq() when an I3C target returns a valid short read response (for example, a 2-byte response to a 5-byte GETMXDS or 3-byte GETM= RL CCC read) or terminates a read early via the T-bit? First, RX_FIFO_WC_MSK in SE_GENI_RX_FIFO_STATUS counts 32-bit FIFO words, a= nd valid bytes in the final partial word are indicated by RX_LAST and RX_LAST_BYTE_VALID_MSK. Computing avail =3D rxcnt * 4 rounds a 2-byte respo= nse up to 4 bytes, so geni_i3c_master_send_ccc_cmd() sets cmd->dests[i].payload.actual_len =3D gi3c->cur_idx to 4 (for GETMXDS, causi= ng i3c_master_getmxds_locked() to fail with -EIO) or 3 (for GETMRL, reading a padding byte as max_ibi_len). Second, M_GP_IRQ_0_EN ("I3C slave early read termination") is included in SE_I3C_ERR and sets gi3c->err =3D -EINVAL in geni_i3c_handle_err(). Because the FIFO RX handler is in an else-if branch after if (m_stat & SE_I3C_ERR .= ..), an early-terminated read fails with -EINVAL and leaves the received words unread in the RX FIFO. > + } else if ((m_stat & M_TX_FIFO_WATERMARK_EN) && > + gi3c->cur_is_write && gi3c->cur_buf) { > + /* FIFO TX handling */ > + int avail =3D gi3c->tx_wm * 4; > + int need =3D gi3c->cur_len - gi3c->cur_idx; > + int n =3D min(need, avail); > + > + if (n > 0) { > + i3c_writel_fifo(gi3c->se.base + SE_GENI_TX_FIFOn, > + (void *)(gi3c->cur_buf + gi3c->cur_idx), n); > + gi3c->cur_idx +=3D n; > + } > + } > + > + if (!dma_mode && gi3c->cur_idx =3D=3D gi3c->cur_len) > + writel_relaxed(0, gi3c->se.base + SE_GENI_TX_WATERMARK_REG); > + } [Severity: High] Can M_TX_FIFO_WATERMARK_EN cause an unhandled interrupt storm if gi3c->cur_= buf becomes NULL while gi3c->cur_idx < gi3c->cur_len? In _i3c_geni_execute_command(): geni_se_setup_m_cmd(&gi3c->se, xfer->m_cmd, xfer->m_param); ... if (xfer->mode =3D=3D GENI_SE_FIFO && len > 0) /* Get FIFO IRQ */ writel_relaxed(1, gi3c->se.base + SE_GENI_TX_WATERMARK_REG); Because geni_se_setup_m_cmd() is called before enabling SE_GENI_TX_WATERMARK_REG without holding gi3c->irq_lock, an immediate error or abort interrupt can run first and clear SE_GENI_TX_WATERMARK_REG, after which _i3c_geni_execute_command() writes 1 to SE_GENI_TX_WATERMARK_REG and sets gi3c->cur_buf =3D NULL. Likewise, on a transfer timeout, _i3c_geni_execute_command() sets gi3c->cur_buf =3D NULL without clearing SE_GENI_TX_WATERMARK_REG. When M_TX_FIFO_WATERMARK_EN then fires in geni_i3c_irq() with gi3c->cur_buf =3D=3D NULL and gi3c->cur_idx < gi3c->cur_len, neither the TX branch nor the cur_idx =3D=3D cur_len check disables SE_GENI_TX_WATERMARK_R= EG, leaving the level-triggered watermark interrupt asserted continuously. > + > + if (m_stat) > + writel_relaxed(m_stat, gi3c->se.base + SE_GENI_M_IRQ_CLEAR); > + > + if (dma_mode) { > + if (dm_tx_st) > + writel_relaxed(dm_tx_st, gi3c->se.base + SE_DMA_TX_IRQ_CLR); > + if (dm_rx_st) > + writel_relaxed(dm_rx_st, gi3c->se.base + SE_DMA_RX_IRQ_CLR); > + } > + > + /* if this is err with done-bit not set, handle that through timeout. */ > + if (m_stat & (M_CMD_DONE_EN | M_CMD_ABORT_EN)) { > + writel_relaxed(0, gi3c->se.base + SE_GENI_TX_WATERMARK_REG); > + complete(&gi3c->done); > + } else if ((dm_tx_st & TX_DMA_DONE) || (dm_rx_st & (RX_DMA_DONE | RX_RE= SET_DONE))) { > + complete(&gi3c->done); > + } > + > + return IRQ_HANDLED; > +} [ ... ] > +static int _i3c_geni_execute_command(struct geni_i3c_dev *gi3c, struct g= eni_i3c_xfer_params *xfer) > +{ [ ... ] > + if (xfer->mode =3D=3D GENI_SE_DMA) { > + if (gi3c->err) { > + if (is_write) > + writel_relaxed(1, gi3c->se.base + SE_DMA_TX_FSM_RST); > + else > + writel_relaxed(1, gi3c->se.base + SE_DMA_RX_FSM_RST); > + > + time_remaining =3D wait_for_completion_timeout(&gi3c->done, XFER_TIME= OUT); > + dev_dbg(gi3c->se.dev, "Timeout completing DMA transfer\n"); > + } > + > + if (is_write) > + geni_se_tx_dma_unprep(&gi3c->se, tx_dma, len); > + else > + geni_se_rx_dma_unprep(&gi3c->se, rx_dma, len); > + } [Severity: High] In _i3c_geni_execute_command() and geni_i3c_irq(), how is gi3c->done synchronized across multi-command loops and DMA FSM resets? 1. Callers only call reinit_completion(&gi3c->done) once before their transfer loops rather than in _i3c_geni_execute_command() before each command and before waiting on SE_DMA_TX_FSM_RST / SE_DMA_RX_FSM_RST. 2. In geni_i3c_irq(), the DMA completion check handles RX_RESET_DONE in dm_rx_st, but omits TX_RESET_DONE in dm_tx_st, so waiting for SE_DMA_TX_FSM_RST in _i3c_geni_execute_command() will always time out before geni_se_tx_dma_unprep() unmaps the buffer. 3. Because m_stat is not masked with SE_GENI_M_IRQ_EN, if M_CMD_DONE_EN is set in m_stat while dma_mode is active, geni_i3c_irq() can complete gi3c->done before TX_DMA_DONE or RX_DMA_DONE fires, causing _i3c_geni_execute_command() to unmap the DMA buffer while DMA is still in flight and leaving an extra completion in gi3c->done for the next comman= d. [ ... ] > +static int geni_i3c_master_priv_xfers(struct i3c_dev_desc *dev, struct i= 3c_xfer *xfers, > + int nxfers, enum i3c_xfer_mode mode) > +{ > + struct i3c_master_controller *m =3D i3c_dev_get_master(dev); > + struct geni_i3c_dev *gi3c =3D to_geni_i3c_master(m); > + bool use_7e =3D false; > + int ret; > + > + scoped_guard(mutex, &gi3c->lock) { [ ... ] > + qcom_geni_i3c_conf(gi3c, PUSH_PULL_MODE); > + > + for (int i =3D 0; i < nxfers; i++) { > + bool stall =3D (i < (nxfers - 1)); > + struct geni_i3c_xfer_params xfer =3D { GENI_SE_FIFO }; > + > + xfer.m_param =3D (stall ? STOP_STRETCH : 0); > + xfer.m_param |=3D FIELD_PREP(SLAVE_ADDR_MASK, dev->info.dyn_addr); > + xfer.m_param |=3D (use_7e) ? USE_7E : 0; > + > + /* use_7e =3D true only for last transfer */ > + use_7e =3D (i =3D=3D nxfers - 1); [Severity: High] In geni_i3c_master_priv_xfers(), use_7e is initialized to false and only set to (i =3D=3D nxfers - 1) after xfer.m_param |=3D (use_7e) ? USE_7E : 0 has = already been evaluated. On iterations i < nxfers - 1, use_7e is false; on the final iteration i =3D=3D nxfers - 1, use_7e is still false when xfer.m_param is built and o= nly becomes true right before the loop exits. As a result, USE_7E is never set = on any transfer (and shouldn't USE_7E be set on the first transfer i =3D=3D 0,= as in geni_i3c_master_send_ccc_cmd() and geni_i3c_perform_daa()?). > + > + if (xfers[i].rnw) { [ ... ] > +static int geni_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, struct i2= c_msg *msgs, int num) > +{ [ ... ] > + for (int i =3D 0; i < num; i++) { > + struct geni_i3c_xfer_params xfer; > + > + xfer.m_cmd =3D (msgs[i].flags & I2C_M_RD) ? I2C_READ : I2C_WRITE; > + xfer.m_param =3D (i < (num - 1)) ? STOP_STRETCH : 0; > + xfer.m_param |=3D FIELD_PREP(SLAVE_ADDR_MASK, msgs[i].addr); > + xfer.mode =3D msgs[i].len > (gi3c->tx_depth / 2) ? > + GENI_SE_DMA : GENI_SE_FIFO; > + if (msgs[i].flags & I2C_M_RD) > + ret =3D i3c_geni_execute_read_command(gi3c, &xfer, msgs[i].buf, > + msgs[i].len); > + else > + ret =3D i3c_geni_execute_write_command(gi3c, &xfer, msgs[i].buf, > + msgs[i].len); > + if (ret) > + break; > + } [Severity: High] In geni_i3c_master_i2c_xfers(), when msgs[i].len > (gi3c->tx_depth / 2), msgs[i].buf is passed directly to GENI_SE_DMA and mapped with dma_map_single() in geni_se_tx_dma_prep() / geni_se_rx_dma_prep(). Since i2c_msg buffers are not guaranteed to be DMA-safe (as noted in the struct i3c_master_controller_ops documentation in include/linux/i3c/master.= h), should this use i2c_get_dma_safe_msg_buf() and i2c_put_dma_safe_msg_buf()? Also, for GENI_SE_DMA transfers: - In _i3c_geni_execute_command(), geni_se_setup_m_cmd() starts the hardware command before geni_se_tx_dma_prep() or geni_se_rx_dma_prep() sets up the DMA transfer (or falls back to GENI_SE_FIFO). - In i3c_geni_resources_init(), avg_bw is set on GENI_TO_CORE and CPU_TO_GENI, but gi3c->se.icc_paths[GENI_TO_DDR].avg_bw is left at 0. [ ... ] > +static int geni_i3c_hw_init(struct geni_i3c_dev *gi3c, struct platform_d= evice *pdev) > +{ > + u32 proto, fifo_disable; > + > + proto =3D geni_se_read_proto(&gi3c->se); > + if (proto !=3D GENI_SE_I3C) { > + geni_se_resources_off(&gi3c->se); > + return dev_err_probe(gi3c->se.dev, -ENXIO, "Invalid proto %d\n", proto= ); > + } > + > + fifo_disable =3D readl_relaxed(gi3c->se.base + GENI_IF_DISABLE_RO); > + if (fifo_disable) { > + geni_se_resources_off(&gi3c->se); > + return dev_err_probe(gi3c->se.dev, -ENXIO, "GPI DMA mode not supported= \n"); > + } [ ... ] > +static int geni_i3c_probe(struct platform_device *pdev) > +{ [ ... ] > + ret =3D geni_se_resources_on(&gi3c->se); > + if (ret) > + return dev_err_probe(&pdev->dev, ret, "Error turning resources ON\n"); > + > + ret =3D geni_i3c_hw_init(gi3c, pdev); > + geni_se_resources_off(&gi3c->se); > + if (ret) > + return ret; [ ... ] > +static int geni_i3c_runtime_suspend(struct device *dev) > +{ > + struct geni_i3c_dev *gi3c =3D dev_get_drvdata(dev); > + > + disable_irq(gi3c->irq); > + geni_se_resources_off(&gi3c->se); > + > + return 0; > +} [Severity: Medium] If geni_i3c_hw_init() fails, it calls geni_se_resources_off(&gi3c->se) befo= re returning, and then geni_i3c_probe() calls geni_se_resources_off(&gi3c->se)= a second time. Won't this underflow the enable/prepare counts on se->clk and the shared QUP wrapper clocks? Also, in geni_i3c_runtime_suspend(), if geni_se_resources_off(&gi3c->se) fails (for instance if pinctrl_pm_select_sleep_state() returns an error before clocks are disabled), should the error be propagated after re-enabli= ng gi3c->irq? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261104111610.3739= 095-1-mukesh.savaliya@oss.qualcomm.com?part=3D2