Re: [PATCH rdma-next 11/23] RDMA/mlx5: Add shadow FIFO infrastructure for UMR completions

[sashiko-bot@kernel.org]

> The UMR CQ is polled by the generic path, which finds the completed
> request by indexing qp->sq.wrid[] with the CQE wqe_counter. A hostile
> NIC can forge it to complete a request other than the one that really
> completed, or one that is not pending at all.
> 
> The UMR QP is RC and signals every WR, so its completions arrive in
> posting order. In adversarial mode, keep a FIFO of the posted UMR
> contexts, so a follow-up patch can check each CQE against the oldest
> pending request instead of trusting it. Each context also records the
> SQ producer counter it was posted at, as its address alone doesn't
> identify the post: it is usually on the stack and reused across posts.
> 
> Nothing consumes the FIFO yet.
> 
> Signed-off-by: Yishai Hadas <yishaih@nvidia.com>

Sashiko has reviewed this patch and found no issues.

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