From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793895095; b=S08EZaGlvR9BM+Z4LiyUxP+H175AFliGuCCNhjFI6Cd/GKLA/7ifPvB66ze9vFOd/P3z b6F4OVDb9g7g5d+6HvG0z4LLWb5I6TgdRF4iegZwV2Wf/r2H954VEABI4iamkRNbXCNh6 sHzhHZ15oGJPYeOqiQiizKR2nFEekQonhSwwUywuYph5gH3Qyn3tzkqRe4ba4juSlmAm5 Sw84uahx4qJtZD8vC979cLm3UCfmn0eLyvw/mGRwG0AyvZ1iX+OBgtVZzZDWlQpAzNQzU DeN6TNV8PcXbrHxMEEKdxQjWTOn1Iv7rapD+g11Nc1lUJgYoNoaD+10lSDTdfOHU7Aw== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793895095; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=eiGQ/KpVn28drSeD6y/HniotQ99k6/RC44L8mEzJXXc=; b=iaCkRMadae1ZJV8jiWP2GG5dgbuae22NCrd65jx0LZRm9svE9V3jCfhsjKeFbAqm2StQ TAe85RwdpVBlJ7u4kQzqmP+lbXvdRtRBPRuIKkZ9JPtZENDbskNI9xvEcPSMSe1TvAwLT 0SgZV99m+7i/FP7SDoOH363UTBNZci35+3a1lM6C4ILdfBtyND9+qgSs3Lx4uvY2rkj8W U5qWtDWrEYGEa3yp8NzBOro5/YU4jK8/PiFRGXOErqScYGVF2BXW1JB83M8H4bUXEvYeu 4jtTttTzq4z9rSyO1CsKIl1a3+UYYldfMvhKdgaiK3k8C4pQ5t5sj0TX/iZ3fnAwhSQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=VJbass+R; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 274F8606A32D for ; Thu, 5 Nov 2026 16:11:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=VJbass+R Received: by smtp.kernel.org (Postfix) with ESMTPSA id 725B81F00919; Thu, 5 Nov 2026 16:11:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793895094; bh=eiGQ/KpVn28drSeD6y/HniotQ99k6/RC44L8mEzJXXc=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=VJbass+RCsxXhH++7ThcFapzSE1a3iQGBUsW8DN5J3GMJuWoQW5rK5/XK24ztkpLb aZ1H5eS9fy15yQsXmDD/5N903tyTk7qgn0pZ8RAPAIOEunUjTaV9ryKWV8YoMqI38P Bw/51ZA81yvOgZqVFRDmOTxVCxSay0ZaiM5tJD0Zc19Mo37ZdlT/dwFBBtMTen5upl gAuVj8EXAgQkoEL6NW8MZPtUm24IELv/SoqssctoV1jD3ZESn3mNOxhzu/KLWqp2RK xlLXFTptZdJ53zbNwE29eOHUL5IUxTzVNtZtofeXaDe1Di1KtjYiekJn43FqdGfU/A HGmNQkrGxu51Q== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v7 2/2] i2c: amlogic: Add Amlogic A9 I2C controller driver Reply-To: sashiko-reviews@lists.linux.dev To: "Xianwei Zhao" Cc: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org In-Reply-To: <20261104-a9-i2c-v7-2-b31f2b53faf4@amlogic.com> References: <20261104-a9-i2c-v7-0-b31f2b53faf4@amlogic.com> <20261104-a9-i2c-v7-2-b31f2b53faf4@amlogic.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Thu, 05 Nov 2026 16:11:34 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 4 potential issue(= s) to consider: - [High] i2c: amlogic: unstopped hw transfer on timeout in aml_i2c_xfer_msg= () - [High] i2c: amlogic-a9: race between complete() and reinit_completion() o= n timeout - [Medium] i2c: amlogic-a9: transfer started before IRQ setup in aml_i2c_do= _start() - [Medium] i2c: amlogic-a9: stale irq_state and edge IRQ miss in aml_i2c_ir= q() -- commit c27eb9a87c5b273047db1979d97f8c36648a9931 Author: Junyi Zhao i2c: amlogic: Add Amlogic A9 I2C controller driver This commit adds an I2C controller driver for Amlogic A9 SoCs along with its Kconfig, Makefile, and MAINTAINERS entries. > diff --git a/drivers/i2c/busses/i2c-amlogic-a9.c b/drivers/i2c/busses/i2c= -amlogic-a9.c > new file mode 100644 > index 0000000000000..d282f275d4d32 > --- /dev/null > +++ b/drivers/i2c/busses/i2c-amlogic-a9.c [ ... ] > +static irqreturn_t aml_i2c_irq(int irqno, void *dev_id) > +{ > + struct aml_i2c *i2c =3D dev_id; > + u8 *buf =3D NULL; > + u32 rd_len, i; > + u32 rd_val; > + u32 irq_state; > + > + spin_lock(&i2c->lock); > + > + irq_state =3D readl(i2c->regs + REG_CFG_IRQ_STATE); > + if (i2c->state =3D=3D A9_STATE_IDLE) { > + dev_warn(i2c->dev, "i2c irq triggered abnormally, irq_state:0x%x,irq_e= n:0x%x\n", > + irq_state, readl(i2c->regs + REG_CFG_IRQ_ENABLE)); > + clear_irq_status(i2c, IRQ_ALL_MASK); > + spin_unlock(&i2c->lock); > + return IRQ_HANDLED; > + } > + > + if (irq_state & A9_TRANS_ERROR) { > + i2c->error =3D -ENXIO; > + goto complete_irq_out; > + } > + > + switch (i2c->state) { > + case A9_STATE_READ: > + buf =3D i2c->msg->buf; > + rd_len =3D min(i2c->msg->len - i2c->pos, A9_I2C_FIFO_DEPTH); > + for (i =3D 0; i < rd_len; i++) { > + rd_val =3D readl(i2c->regs + REG_CFG_RX); > + buf[i2c->pos++] =3D rd_val & TX_RX_DATA; > + } > + /* Rx must clear thresh after read fifo */ > + clear_irq_status(i2c, A9_RX_THRESH_READ); > + break; > + case A9_STATE_WRITE: > + aml_i2c_prepare_xfer(i2c, A9_FIFO_FILL_HALF); > + if (i2c->pos =3D=3D i2c->msg->len) > + aml_i2c_set_mask(i2c, REG_CFG_IRQ_ENABLE, A9_TX_THRESH_WRITE, 0); > + /* Tx must clear thresh after write fifo */ > + clear_irq_status(i2c, A9_TX_THRESH_WRITE); > + break; > + default: > + break; > + } > + > + if (!(irq_state & A9_TRANS_DONE) || > + (i2c->state =3D=3D A9_STATE_READ && i2c->pos < i2c->msg->len)) { > + spin_unlock(&i2c->lock); > + return IRQ_HANDLED; > + } [Severity: Medium] As reported by Sashiko on v2 [1], in aml_i2c_irq(), can multi-chunk I2C read transfers (where msg->len > A9_I2C_FIFO_DEPTH) miss the transfer completion interrupt and time out in wait_for_completion_timeout()? In Documentation/devicetree/bindings/i2c/amlogic,a9-i2c.yaml, the controller interrupt is configured as rising-edge triggered (IRQ_TYPE_EDGE_RISING), wh= ich requires a 0-to-1 signal transition to latch a new pending interrupt in the GIC. For a read transfer with msg->len > A9_I2C_FIFO_DEPTH, aml_i2c_do_start() enables A9_RX_THRESH_READ in REG_CFG_IRQ_ENABLE alongside A9_PHY_DONE and A9_NCK_ERROR. Unlike A9_STATE_WRITE, which disables A9_TX_THRESH_WRITE once the final bytes are written to the TX FIFO, A9_STATE_READ never disables A9_RX_THRESH_READ when the remaining bytes fit in a single FIFO chunk. Because irq_state =3D readl(i2c->regs + REG_CFG_IRQ_STATE) is sampled only = once at the start of aml_i2c_irq() before reading up to 32 bytes from REG_CFG_RX: 1. When msg->len is a multiple of 32, the 32nd byte of the final chunk can trigger A9_RX_THRESH_READ before the I2C NACK and STOP condition finish on = the bus. If A9_PHY_DONE asserts in REG_CFG_IRQ_STATE during the loop reading REG_CFG_RX before clear_irq_status(i2c, A9_RX_THRESH_READ) runs, the controller interrupt output stays continuously high without generating a new rising edge, while aml_i2c_irq() checks the stale irq_state snapshot and returns early without completing i2c->done even though i2c->pos =3D=3D i2c->msg->len. 2. Similarly, if both A9_RX_THRESH_READ and A9_PHY_DONE are asserted in REG_CFG_IRQ_STATE when more than 32 bytes remain (so i2c->pos < i2c->msg->l= en after reading one 32-byte chunk), aml_i2c_irq() clears only A9_RX_THRESH_RE= AD and returns early with A9_PHY_DONE still asserted and fewer than 32 bytes l= eft in the RX FIFO. Because A9_PHY_DONE remains asserted continuously, no new 0-to-1 edge occurs to re-trigger the interrupt handler for the remaining bytes. > + > +complete_irq_out: > + i2c->state =3D A9_STATE_IDLE; > + reset_fifo_pos(i2c); > + aml_i2c_set_mask(i2c, REG_CFG_IRQ_ENABLE, A9_RX_THRESH_READ | A9_TX_THR= ESH_WRITE, 0); > + clear_irq_status(i2c, IRQ_ALL_MASK); > + spin_unlock(&i2c->lock); > + complete(&i2c->done); > + > + return IRQ_HANDLED; > +} > + > +static void aml_i2c_do_start(struct aml_i2c *i2c, struct i2c_msg *msg) > +{ > + unsigned int reg_val; > + unsigned int trans_len; > + > + trans_len =3D msg->len; > + reg_val =3D (unsigned int)(((msg->addr & 0x7f) << START_SADDR_SHIFT) | > + ((msg->flags & I2C_M_RD) ? START_READ : 0) | > + ((trans_len & 0xfff) << START_LEN_SHIFT) | START_START); > + aml_i2c_set_mask(i2c, REG_CFG_START, > + START_START | START_SLAVE_ADDR | START_READ | START_LEN, reg_val); > + clear_irq_status(i2c, IRQ_ALL_MASK); > + /* enable thresh mode */ > + if (trans_len > A9_I2C_FIFO_DEPTH) { > + reg_val =3D (msg->flags & I2C_M_RD) ? A9_RX_THRESH_READ : A9_TX_THRESH= _WRITE; > + aml_i2c_set_mask(i2c, REG_CFG_IRQ_ENABLE, > + A9_RX_THRESH_READ | A9_TX_THRESH_WRITE, reg_val); > + } > +} [Severity: Medium] As reported by Sashiko on v2 [2], in aml_i2c_do_start(), could starting the hardware transfer before clearing REG_CFG_IRQ_STATE and enabling the FIFO threshold interrupts lose a fast completion or NACK status bit? In aml_i2c_xfer() -> aml_i2c_xfer_msg() -> aml_i2c_do_start(), aml_i2c_set_mask() writes START_START to REG_CFG_START while A9_ENABLE_IRQ_= BIT (A9_NCK_ERROR | A9_PHY_DONE) is already enabled in REG_CFG_IRQ_ENABLE, befo= re clear_irq_status(i2c, IRQ_ALL_MASK) is called and before A9_RX_THRESH_READ = or A9_TX_THRESH_WRITE is enabled. If execution is delayed between writing REG_CFG_START and writing REG_CFG_IRQ_STATE (for example due to task preemption while holding spinloc= k_t on PREEMPT_RT, vCPU preemption, or interrupt/firmware latency), the hardware can assert A9_NCK_ERROR or A9_PHY_DONE and have it immediately wiped out by clear_irq_status(i2c, IRQ_ALL_MASK) before aml_i2c_irq() acquires i2c->lock and reads REG_CFG_IRQ_STATE. When aml_i2c_irq() then runs, it sees irq_state =3D=3D 0, misses A9_TRANS_ERROR, touches REG_CFG_RX or REG_CFG_TX unconditi= onally, and exits at !(irq_state & A9_TRANS_DONE) without calling complete(&i2c->do= ne), causing wait_for_completion_timeout() in aml_i2c_xfer_msg() to hang for 500= ms and return -ETIMEDOUT. Should clear_irq_status(i2c, IRQ_ALL_MASK) and the REG_CFG_IRQ_ENABLE setup happen before asserting START_START in REG_CFG_START? > + > +static int aml_i2c_xfer_msg(struct aml_i2c *i2c, struct i2c_msg *msg, bo= ol last) > +{ > + unsigned long time_left, flags; > + > + i2c->msg =3D msg; > + i2c->pos =3D 0; > + i2c->error =3D 0; > + > + spin_lock_irqsave(&i2c->lock, flags); > + i2c->state =3D (msg->flags & I2C_M_RD) ? A9_STATE_READ : A9_STATE_WRITE; > + aml_i2c_prepare_xfer(i2c, A9_FIFO_FILL_FULL); > + reinit_completion(&i2c->done); [Severity: High] Can a late interrupt from a completing transfer race with the timeout path = and a subsequent call to reinit_completion(&i2c->done) in aml_i2c_xfer_msg()? In aml_i2c_irq(), the complete_irq_out path sets i2c->state =3D A9_STATE_ID= LE, releases i2c->lock via spin_unlock(&i2c->lock), and then calls complete(&i2c->done) outside i2c->lock. Meanwhile, aml_i2c_xfer_msg() initializes i2c->msg, i2c->pos, and i2c->error before acquiring i2c->lock a= nd calling reinit_completion(&i2c->done). If a transfer finishes on CPU 1 just as wait_for_completion_timeout() expir= es on CPU 0: CPU 1 (aml_i2c_irq) CPU 0 (aml_i2c_xfer_msg) ------------------- ------------------------ spin_unlock(&i2c->lock); /* !time_left timeout path */ spin_lock_irqsave(&i2c->lock, flags); ... spin_unlock_irqrestore(&i2c->lock, flags= ); return -ETIMEDOUT; /* next message starts */ i2c->msg =3D msg; spin_lock_irqsave(&i2c->lock, flags); i2c->state =3D A9_STATE_READ; reinit_completion(&i2c->done); aml_i2c_do_start(i2c, msg); spin_unlock_irqrestore(&i2c->lock, flags= ); wait_for_completion_timeout(&i2c->done, = ...); complete(&i2c->done); In this case, CPU 1's delayed complete(&i2c->done) wakes wait_for_completion_timeout() immediately while the new transfer is still active in hardware. That allows aml_i2c_xfer_msg() to return early while aml_i2c_irq() can still access i2c->msg and write to i2c->msg->buf after the caller frees or pops the buffer, or while the next message in aml_i2c_xfer() overwrites i2c->msg, i2c->pos, and i2c->error without holding i2c->lock. Should complete(&i2c->done) be called while holding i2c->lock, and should i2c->msg, i2c->pos, and i2c->error be accessed under i2c->lock? > + > + aml_i2c_set_mask(i2c, REG_CFG_BUS, BUS_NO_STOP, (last ? 0 : BUS_NO_STOP= )); > + > + /* Start the transfer */ > + aml_i2c_do_start(i2c, msg); > + spin_unlock_irqrestore(&i2c->lock, flags); > + > + time_left =3D msecs_to_jiffies(I2C_TIMEOUT_MS); > + time_left =3D wait_for_completion_timeout(&i2c->done, time_left); > + > + /* > + * Protect access to i2c struct and registers from interrupt > + * handlers triggered by a transfer terminated after the > + * timeout period > + */ > + > + if (!time_left) { > + spin_lock_irqsave(&i2c->lock, flags); > + i2c->state =3D A9_STATE_IDLE; > + aml_i2c_set_mask(i2c, REG_CFG_IRQ_ENABLE, > + A9_RX_THRESH_READ | A9_TX_THRESH_WRITE, 0); > + clear_irq_status(i2c, IRQ_ALL_MASK); > + reset_fifo_pos(i2c); > + spin_unlock_irqrestore(&i2c->lock, flags); > + return -ETIMEDOUT; > + } [Severity: High] As reported by Sashiko on v2 [3], when wait_for_completion_timeout() expires in aml_i2c_xfer_msg(), does the timeout cleanup leave the hardware transfer running on the bus? In the !time_left block, the driver resets i2c->state =3D A9_STATE_IDLE, disables A9_RX_THRESH_READ | A9_TX_THRESH_WRITE in REG_CFG_IRQ_ENABLE, clea= rs REG_CFG_IRQ_STATE, and calls reset_fifo_pos(i2c), but it never clears START_START in REG_CFG_START (or otherwise halts the controller) while A9_ENABLE_IRQ_BIT (A9_NCK_ERROR | A9_PHY_DONE) remains enabled in REG_CFG_IRQ_ENABLE. If a stalled bus transfer continues shifting bytes after reset_fifo_pos(i2c= ), it will advance the hardware FIFO pointers before the next transfer calls aml_i2c_prepare_xfer(). Furthermore, if the stalled transfer finishes (A9_PHY_DONE) or NACKs (A9_NCK_ERROR) after a subsequent call to aml_i2c_xfer_msg() has set i2c->state to A9_STATE_READ or A9_STATE_WRITE and released i2c->lock, aml_i2c_irq() will service that stale interrupt against the new i2c->msg, corrupting i2c->msg->buf, i2c->pos, and i2c->error and prematurely completing i2c->done. Should the timeout path clear START_START in REG_CFG_START to abort the act= ive hardware transfer under i2c->lock? [1] https://lore.kernel.org/r/sashiko-outbox-181284@kernel.org [2] https://lore.kernel.org/r/sashiko-outbox-181284@kernel.org [3] https://lore.kernel.org/r/sashiko-outbox-181284@kernel.org --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261104-a9-i2c-v7-= 0-b31f2b53faf4@amlogic.com?part=3D2 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63539606A326 for ; Thu, 5 Nov 2026 16:11:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=hvLNgOIt; dkim=fail reason="signature verification failed" (2048-bit key, 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helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xP03x-00000009YZv-1ej0; Thu, 05 Nov 2026 16:11:41 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xP03r-00000009YZB-1DcC for linux-amlogic@lists.infradead.org; Thu, 05 Nov 2026 16:11:36 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id D2894407E7; Thu, 5 Nov 2026 16:11:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 725B81F00919; Thu, 5 Nov 2026 16:11:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793895094; bh=eiGQ/KpVn28drSeD6y/HniotQ99k6/RC44L8mEzJXXc=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=VJbass+RCsxXhH++7ThcFapzSE1a3iQGBUsW8DN5J3GMJuWoQW5rK5/XK24ztkpLb aZ1H5eS9fy15yQsXmDD/5N903tyTk7qgn0pZ8RAPAIOEunUjTaV9ryKWV8YoMqI38P Bw/51ZA81yvOgZqVFRDmOTxVCxSay0ZaiM5tJD0Zc19Mo37ZdlT/dwFBBtMTen5upl gAuVj8EXAgQkoEL6NW8MZPtUm24IELv/SoqssctoV1jD3ZESn3mNOxhzu/KLWqp2RK xlLXFTptZdJ53zbNwE29eOHUL5IUxTzVNtZtofeXaDe1Di1KtjYiekJn43FqdGfU/A HGmNQkrGxu51Q== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v7 2/2] i2c: amlogic: Add Amlogic A9 I2C controller driver To: "Xianwei Zhao" Cc: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org In-Reply-To: <20261104-a9-i2c-v7-2-b31f2b53faf4@amlogic.com> References: <20261104-a9-i2c-v7-0-b31f2b53faf4@amlogic.com> <20261104-a9-i2c-v7-2-b31f2b53faf4@amlogic.com> Date: Thu, 05 Nov 2026 16:11:34 +0000 X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-amlogic" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg NCBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIGkyYzogYW1sb2dpYzog dW5zdG9wcGVkIGh3IHRyYW5zZmVyIG9uIHRpbWVvdXQgaW4gYW1sX2kyY194ZmVyX21zZygpCi0g W0hpZ2hdIGkyYzogYW1sb2dpYy1hOTogcmFjZSBiZXR3ZWVuIGNvbXBsZXRlKCkgYW5kIHJlaW5p dF9jb21wbGV0aW9uKCkgb24gdGltZW91dAotIFtNZWRpdW1dIGkyYzogYW1sb2dpYy1hOTogdHJh bnNmZXIgc3RhcnRlZCBiZWZvcmUgSVJRIHNldHVwIGluIGFtbF9pMmNfZG9fc3RhcnQoKQotIFtN ZWRpdW1dIGkyYzogYW1sb2dpYy1hOTogc3RhbGUgaXJxX3N0YXRlIGFuZCBlZGdlIElSUSBtaXNz IGluIGFtbF9pMmNfaXJxKCkKLS0KCmNvbW1pdCBjMjdlYjlhODdjNWIyNzMwNDdkYjE5NzlkOTdm OGMzNjY0OGE5OTMxCkF1dGhvcjogSnVueWkgWmhhbyA8anVueWkuemhhb0BhbWxvZ2ljLmNvbT4K CmkyYzogYW1sb2dpYzogQWRkIEFtbG9naWMgQTkgSTJDIGNvbnRyb2xsZXIgZHJpdmVyCgpUaGlz IGNvbW1pdCBhZGRzIGFuIEkyQyBjb250cm9sbGVyIGRyaXZlciBmb3IgQW1sb2dpYyBBOSBTb0Nz IGFsb25nIHdpdGggaXRzCktjb25maWcsIE1ha2VmaWxlLCBhbmQgTUFJTlRBSU5FUlMgZW50cmll cy4KCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvaTJjL2J1c3Nlcy9pMmMtYW1sb2dpYy1hOS5jIGIv ZHJpdmVycy9pMmMvYnVzc2VzL2kyYy1hbWxvZ2ljLWE5LmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0 NAo+IGluZGV4IDAwMDAwMDAwMDAwMDAuLmQyODJmMjc1ZDRkMzIKPiAtLS0gL2Rldi9udWxsCj4g KysrIGIvZHJpdmVycy9pMmMvYnVzc2VzL2kyYy1hbWxvZ2ljLWE5LmMKWyAuLi4gXQo+ICtzdGF0 aWMgaXJxcmV0dXJuX3QgYW1sX2kyY19pcnEoaW50IGlycW5vLCB2b2lkICpkZXZfaWQpCj4gK3sK PiArCXN0cnVjdCBhbWxfaTJjICppMmMgPSBkZXZfaWQ7Cj4gKwl1OCAqYnVmID0gTlVMTDsKPiAr CXUzMiByZF9sZW4sIGk7Cj4gKwl1MzIgcmRfdmFsOwo+ICsJdTMyIGlycV9zdGF0ZTsKPiArCj4g KwlzcGluX2xvY2soJmkyYy0+bG9jayk7Cj4gKwo+ICsJaXJxX3N0YXRlID0gcmVhZGwoaTJjLT5y ZWdzICsgUkVHX0NGR19JUlFfU1RBVEUpOwo+ICsJaWYgKGkyYy0+c3RhdGUgPT0gQTlfU1RBVEVf SURMRSkgewo+ICsJCWRldl93YXJuKGkyYy0+ZGV2LCAiaTJjIGlycSB0cmlnZ2VyZWQgYWJub3Jt YWxseSwgaXJxX3N0YXRlOjB4JXgsaXJxX2VuOjB4JXhcbiIsCj4gKwkJCSBpcnFfc3RhdGUsIHJl YWRsKGkyYy0+cmVncyArIFJFR19DRkdfSVJRX0VOQUJMRSkpOwo+ICsJCWNsZWFyX2lycV9zdGF0 dXMoaTJjLCBJUlFfQUxMX01BU0spOwo+ICsJCXNwaW5fdW5sb2NrKCZpMmMtPmxvY2spOwo+ICsJ CXJldHVybiBJUlFfSEFORExFRDsKPiArCX0KPiArCj4gKwlpZiAoaXJxX3N0YXRlICYgQTlfVFJB TlNfRVJST1IpIHsKPiArCQlpMmMtPmVycm9yID0gLUVOWElPOwo+ICsJCWdvdG8gY29tcGxldGVf aXJxX291dDsKPiArCX0KPiArCj4gKwlzd2l0Y2ggKGkyYy0+c3RhdGUpIHsKPiArCWNhc2UgQTlf U1RBVEVfUkVBRDoKPiArCQlidWYgPSBpMmMtPm1zZy0+YnVmOwo+ICsJCXJkX2xlbiA9IG1pbihp MmMtPm1zZy0+bGVuIC0gaTJjLT5wb3MsIEE5X0kyQ19GSUZPX0RFUFRIKTsKPiArCQlmb3IgKGkg PSAwOyBpIDwgcmRfbGVuOyBpKyspIHsKPiArCQkJcmRfdmFsID0gcmVhZGwoaTJjLT5yZWdzICsg UkVHX0NGR19SWCk7Cj4gKwkJCWJ1ZltpMmMtPnBvcysrXSA9IHJkX3ZhbCAmIFRYX1JYX0RBVEE7 Cj4gKwkJfQo+ICsJCS8qIFJ4IG11c3QgY2xlYXIgdGhyZXNoIGFmdGVyIHJlYWQgZmlmbyAqLwo+ ICsJCWNsZWFyX2lycV9zdGF0dXMoaTJjLCBBOV9SWF9USFJFU0hfUkVBRCk7Cj4gKwkJYnJlYWs7 Cj4gKwljYXNlIEE5X1NUQVRFX1dSSVRFOgo+ICsJCWFtbF9pMmNfcHJlcGFyZV94ZmVyKGkyYywg QTlfRklGT19GSUxMX0hBTEYpOwo+ICsJCWlmIChpMmMtPnBvcyA9PSBpMmMtPm1zZy0+bGVuKQo+ ICsJCQlhbWxfaTJjX3NldF9tYXNrKGkyYywgUkVHX0NGR19JUlFfRU5BQkxFLCBBOV9UWF9USFJF U0hfV1JJVEUsIDApOwo+ICsJCS8qIFR4IG11c3QgY2xlYXIgdGhyZXNoIGFmdGVyIHdyaXRlIGZp Zm8gKi8KPiArCQljbGVhcl9pcnFfc3RhdHVzKGkyYywgQTlfVFhfVEhSRVNIX1dSSVRFKTsKPiAr CQlicmVhazsKPiArCWRlZmF1bHQ6Cj4gKwkJYnJlYWs7Cj4gKwl9Cj4gKwo+ICsJaWYgKCEoaXJx X3N0YXRlICYgQTlfVFJBTlNfRE9ORSkgfHwKPiArCSAgICAoaTJjLT5zdGF0ZSA9PSBBOV9TVEFU RV9SRUFEICYmIGkyYy0+cG9zIDwgaTJjLT5tc2ctPmxlbikpIHsKPiArCQlzcGluX3VubG9jaygm aTJjLT5sb2NrKTsKPiArCQlyZXR1cm4gSVJRX0hBTkRMRUQ7Cj4gKwl9CgpbU2V2ZXJpdHk6IE1l ZGl1bV0KQXMgcmVwb3J0ZWQgYnkgU2FzaGlrbyBvbiB2MiBbMV0sIGluIGFtbF9pMmNfaXJxKCks IGNhbiBtdWx0aS1jaHVuayBJMkMgcmVhZAp0cmFuc2ZlcnMgKHdoZXJlIG1zZy0+bGVuID4gQTlf STJDX0ZJRk9fREVQVEgpIG1pc3MgdGhlIHRyYW5zZmVyIGNvbXBsZXRpb24KaW50ZXJydXB0IGFu ZCB0aW1lIG91dCBpbiB3YWl0X2Zvcl9jb21wbGV0aW9uX3RpbWVvdXQoKT8KCkluIERvY3VtZW50 YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9pMmMvYW1sb2dpYyxhOS1pMmMueWFtbCwgdGhlIGNv bnRyb2xsZXIKaW50ZXJydXB0IGlzIGNvbmZpZ3VyZWQgYXMgcmlzaW5nLWVkZ2UgdHJpZ2dlcmVk IChJUlFfVFlQRV9FREdFX1JJU0lORyksIHdoaWNoCnJlcXVpcmVzIGEgMC10by0xIHNpZ25hbCB0 cmFuc2l0aW9uIHRvIGxhdGNoIGEgbmV3IHBlbmRpbmcgaW50ZXJydXB0IGluIHRoZQpHSUMuCgpG b3IgYSByZWFkIHRyYW5zZmVyIHdpdGggbXNnLT5sZW4gPiBBOV9JMkNfRklGT19ERVBUSCwgYW1s X2kyY19kb19zdGFydCgpCmVuYWJsZXMgQTlfUlhfVEhSRVNIX1JFQUQgaW4gUkVHX0NGR19JUlFf RU5BQkxFIGFsb25nc2lkZSBBOV9QSFlfRE9ORSBhbmQKQTlfTkNLX0VSUk9SLiBVbmxpa2UgQTlf U1RBVEVfV1JJVEUsIHdoaWNoIGRpc2FibGVzIEE5X1RYX1RIUkVTSF9XUklURSBvbmNlCnRoZSBm aW5hbCBieXRlcyBhcmUgd3JpdHRlbiB0byB0aGUgVFggRklGTywgQTlfU1RBVEVfUkVBRCBuZXZl ciBkaXNhYmxlcwpBOV9SWF9USFJFU0hfUkVBRCB3aGVuIHRoZSByZW1haW5pbmcgYnl0ZXMgZml0 IGluIGEgc2luZ2xlIEZJRk8gY2h1bmsuCgpCZWNhdXNlIGlycV9zdGF0ZSA9IHJlYWRsKGkyYy0+ cmVncyArIFJFR19DRkdfSVJRX1NUQVRFKSBpcyBzYW1wbGVkIG9ubHkgb25jZQphdCB0aGUgc3Rh cnQgb2YgYW1sX2kyY19pcnEoKSBiZWZvcmUgcmVhZGluZyB1cCB0byAzMiBieXRlcyBmcm9tIFJF R19DRkdfUlg6CgoxLiBXaGVuIG1zZy0+bGVuIGlzIGEgbXVsdGlwbGUgb2YgMzIsIHRoZSAzMm5k IGJ5dGUgb2YgdGhlIGZpbmFsIGNodW5rIGNhbgp0cmlnZ2VyIEE5X1JYX1RIUkVTSF9SRUFEIGJl Zm9yZSB0aGUgSTJDIE5BQ0sgYW5kIFNUT1AgY29uZGl0aW9uIGZpbmlzaCBvbiB0aGUKYnVzLiBJ ZiBBOV9QSFlfRE9ORSBhc3NlcnRzIGluIFJFR19DRkdfSVJRX1NUQVRFIGR1cmluZyB0aGUgbG9v cCByZWFkaW5nClJFR19DRkdfUlggYmVmb3JlIGNsZWFyX2lycV9zdGF0dXMoaTJjLCBBOV9SWF9U SFJFU0hfUkVBRCkgcnVucywgdGhlCmNvbnRyb2xsZXIgaW50ZXJydXB0IG91dHB1dCBzdGF5cyBj b250aW51b3VzbHkgaGlnaCB3aXRob3V0IGdlbmVyYXRpbmcgYSBuZXcKcmlzaW5nIGVkZ2UsIHdo aWxlIGFtbF9pMmNfaXJxKCkgY2hlY2tzIHRoZSBzdGFsZSBpcnFfc3RhdGUgc25hcHNob3QgYW5k CnJldHVybnMgZWFybHkgd2l0aG91dCBjb21wbGV0aW5nIGkyYy0+ZG9uZSBldmVuIHRob3VnaCBp MmMtPnBvcyA9PQppMmMtPm1zZy0+bGVuLgoKMi4gU2ltaWxhcmx5LCBpZiBib3RoIEE5X1JYX1RI UkVTSF9SRUFEIGFuZCBBOV9QSFlfRE9ORSBhcmUgYXNzZXJ0ZWQgaW4KUkVHX0NGR19JUlFfU1RB VEUgd2hlbiBtb3JlIHRoYW4gMzIgYnl0ZXMgcmVtYWluIChzbyBpMmMtPnBvcyA8IGkyYy0+bXNn LT5sZW4KYWZ0ZXIgcmVhZGluZyBvbmUgMzItYnl0ZSBjaHVuayksIGFtbF9pMmNfaXJxKCkgY2xl YXJzIG9ubHkgQTlfUlhfVEhSRVNIX1JFQUQKYW5kIHJldHVybnMgZWFybHkgd2l0aCBBOV9QSFlf RE9ORSBzdGlsbCBhc3NlcnRlZCBhbmQgZmV3ZXIgdGhhbiAzMiBieXRlcyBsZWZ0CmluIHRoZSBS WCBGSUZPLiBCZWNhdXNlIEE5X1BIWV9ET05FIHJlbWFpbnMgYXNzZXJ0ZWQgY29udGludW91c2x5 LCBubyBuZXcKMC10by0xIGVkZ2Ugb2NjdXJzIHRvIHJlLXRyaWdnZXIgdGhlIGludGVycnVwdCBo YW5kbGVyIGZvciB0aGUgcmVtYWluaW5nCmJ5dGVzLgoKPiArCj4gK2NvbXBsZXRlX2lycV9vdXQ6 Cj4gKwlpMmMtPnN0YXRlID0gQTlfU1RBVEVfSURMRTsKPiArCXJlc2V0X2ZpZm9fcG9zKGkyYyk7 Cj4gKwlhbWxfaTJjX3NldF9tYXNrKGkyYywgUkVHX0NGR19JUlFfRU5BQkxFLCBBOV9SWF9USFJF U0hfUkVBRCB8IEE5X1RYX1RIUkVTSF9XUklURSwgMCk7Cj4gKwljbGVhcl9pcnFfc3RhdHVzKGky YywgSVJRX0FMTF9NQVNLKTsKPiArCXNwaW5fdW5sb2NrKCZpMmMtPmxvY2spOwo+ICsJY29tcGxl dGUoJmkyYy0+ZG9uZSk7Cj4gKwo+ICsJcmV0dXJuIElSUV9IQU5ETEVEOwo+ICt9Cj4gKwo+ICtz dGF0aWMgdm9pZCBhbWxfaTJjX2RvX3N0YXJ0KHN0cnVjdCBhbWxfaTJjICppMmMsIHN0cnVjdCBp MmNfbXNnICptc2cpCj4gK3sKPiArCXVuc2lnbmVkIGludCByZWdfdmFsOwo+ICsJdW5zaWduZWQg aW50IHRyYW5zX2xlbjsKPiArCj4gKwl0cmFuc19sZW4gPSBtc2ctPmxlbjsKPiArCXJlZ192YWwg PSAodW5zaWduZWQgaW50KSgoKG1zZy0+YWRkciAmIDB4N2YpIDw8IFNUQVJUX1NBRERSX1NISUZU KSB8Cj4gKwkJCQkoKG1zZy0+ZmxhZ3MgJiBJMkNfTV9SRCkgPyBTVEFSVF9SRUFEIDogMCkgfAo+ ICsJCQkJKCh0cmFuc19sZW4gJiAweGZmZikgPDwgU1RBUlRfTEVOX1NISUZUKSB8IFNUQVJUX1NU QVJUKTsKPiArCWFtbF9pMmNfc2V0X21hc2soaTJjLCBSRUdfQ0ZHX1NUQVJULAo+ICsJCQkgU1RB UlRfU1RBUlQgfCBTVEFSVF9TTEFWRV9BRERSIHwgU1RBUlRfUkVBRCB8IFNUQVJUX0xFTiwgcmVn X3ZhbCk7Cj4gKwljbGVhcl9pcnFfc3RhdHVzKGkyYywgSVJRX0FMTF9NQVNLKTsKPiArCS8qIGVu YWJsZSB0aHJlc2ggbW9kZSAqLwo+ICsJaWYgKHRyYW5zX2xlbiA+IEE5X0kyQ19GSUZPX0RFUFRI KSB7Cj4gKwkJcmVnX3ZhbCA9IChtc2ctPmZsYWdzICYgSTJDX01fUkQpID8gQTlfUlhfVEhSRVNI X1JFQUQgOiBBOV9UWF9USFJFU0hfV1JJVEU7Cj4gKwkJYW1sX2kyY19zZXRfbWFzayhpMmMsIFJF R19DRkdfSVJRX0VOQUJMRSwKPiArCQkJCSBBOV9SWF9USFJFU0hfUkVBRCB8IEE5X1RYX1RIUkVT SF9XUklURSwgcmVnX3ZhbCk7Cj4gKwl9Cj4gK30KCltTZXZlcml0eTogTWVkaXVtXQpBcyByZXBv cnRlZCBieSBTYXNoaWtvIG9uIHYyIFsyXSwgaW4gYW1sX2kyY19kb19zdGFydCgpLCBjb3VsZCBz dGFydGluZyB0aGUKaGFyZHdhcmUgdHJhbnNmZXIgYmVmb3JlIGNsZWFyaW5nIFJFR19DRkdfSVJR X1NUQVRFIGFuZCBlbmFibGluZyB0aGUgRklGTwp0aHJlc2hvbGQgaW50ZXJydXB0cyBsb3NlIGEg ZmFzdCBjb21wbGV0aW9uIG9yIE5BQ0sgc3RhdHVzIGJpdD8KCkluIGFtbF9pMmNfeGZlcigpIC0+ IGFtbF9pMmNfeGZlcl9tc2coKSAtPiBhbWxfaTJjX2RvX3N0YXJ0KCksCmFtbF9pMmNfc2V0X21h c2soKSB3cml0ZXMgU1RBUlRfU1RBUlQgdG8gUkVHX0NGR19TVEFSVCB3aGlsZSBBOV9FTkFCTEVf SVJRX0JJVAooQTlfTkNLX0VSUk9SIHwgQTlfUEhZX0RPTkUpIGlzIGFscmVhZHkgZW5hYmxlZCBp biBSRUdfQ0ZHX0lSUV9FTkFCTEUsIGJlZm9yZQpjbGVhcl9pcnFfc3RhdHVzKGkyYywgSVJRX0FM TF9NQVNLKSBpcyBjYWxsZWQgYW5kIGJlZm9yZSBBOV9SWF9USFJFU0hfUkVBRCBvcgpBOV9UWF9U SFJFU0hfV1JJVEUgaXMgZW5hYmxlZC4KCklmIGV4ZWN1dGlvbiBpcyBkZWxheWVkIGJldHdlZW4g d3JpdGluZyBSRUdfQ0ZHX1NUQVJUIGFuZCB3cml0aW5nClJFR19DRkdfSVJRX1NUQVRFIChmb3Ig ZXhhbXBsZSBkdWUgdG8gdGFzayBwcmVlbXB0aW9uIHdoaWxlIGhvbGRpbmcgc3BpbmxvY2tfdApv biBQUkVFTVBUX1JULCB2Q1BVIHByZWVtcHRpb24sIG9yIGludGVycnVwdC9maXJtd2FyZSBsYXRl bmN5KSwgdGhlIGhhcmR3YXJlCmNhbiBhc3NlcnQgQTlfTkNLX0VSUk9SIG9yIEE5X1BIWV9ET05F IGFuZCBoYXZlIGl0IGltbWVkaWF0ZWx5IHdpcGVkIG91dCBieQpjbGVhcl9pcnFfc3RhdHVzKGky YywgSVJRX0FMTF9NQVNLKSBiZWZvcmUgYW1sX2kyY19pcnEoKSBhY3F1aXJlcyBpMmMtPmxvY2sK YW5kIHJlYWRzIFJFR19DRkdfSVJRX1NUQVRFLiBXaGVuIGFtbF9pMmNfaXJxKCkgdGhlbiBydW5z LCBpdCBzZWVzIGlycV9zdGF0ZQo9PSAwLCBtaXNzZXMgQTlfVFJBTlNfRVJST1IsIHRvdWNoZXMg UkVHX0NGR19SWCBvciBSRUdfQ0ZHX1RYIHVuY29uZGl0aW9uYWxseSwKYW5kIGV4aXRzIGF0ICEo aXJxX3N0YXRlICYgQTlfVFJBTlNfRE9ORSkgd2l0aG91dCBjYWxsaW5nIGNvbXBsZXRlKCZpMmMt PmRvbmUpLApjYXVzaW5nIHdhaXRfZm9yX2NvbXBsZXRpb25fdGltZW91dCgpIGluIGFtbF9pMmNf eGZlcl9tc2coKSB0byBoYW5nIGZvciA1MDAgbXMKYW5kIHJldHVybiAtRVRJTUVET1VULgoKU2hv dWxkIGNsZWFyX2lycV9zdGF0dXMoaTJjLCBJUlFfQUxMX01BU0spIGFuZCB0aGUgUkVHX0NGR19J UlFfRU5BQkxFIHNldHVwCmhhcHBlbiBiZWZvcmUgYXNzZXJ0aW5nIFNUQVJUX1NUQVJUIGluIFJF R19DRkdfU1RBUlQ/Cgo+ICsKPiArc3RhdGljIGludCBhbWxfaTJjX3hmZXJfbXNnKHN0cnVjdCBh bWxfaTJjICppMmMsIHN0cnVjdCBpMmNfbXNnICptc2csIGJvb2wgbGFzdCkKPiArewo+ICsJdW5z aWduZWQgbG9uZyB0aW1lX2xlZnQsIGZsYWdzOwo+ICsKPiArCWkyYy0+bXNnID0gbXNnOwo+ICsJ aTJjLT5wb3MgPSAwOwo+ICsJaTJjLT5lcnJvciA9IDA7Cj4gKwo+ICsJc3Bpbl9sb2NrX2lycXNh dmUoJmkyYy0+bG9jaywgZmxhZ3MpOwo+ICsJaTJjLT5zdGF0ZSA9IChtc2ctPmZsYWdzICYgSTJD X01fUkQpID8gQTlfU1RBVEVfUkVBRCA6IEE5X1NUQVRFX1dSSVRFOwo+ICsJYW1sX2kyY19wcmVw YXJlX3hmZXIoaTJjLCBBOV9GSUZPX0ZJTExfRlVMTCk7Cj4gKwlyZWluaXRfY29tcGxldGlvbigm aTJjLT5kb25lKTsKCltTZXZlcml0eTogSGlnaF0KQ2FuIGEgbGF0ZSBpbnRlcnJ1cHQgZnJvbSBh IGNvbXBsZXRpbmcgdHJhbnNmZXIgcmFjZSB3aXRoIHRoZSB0aW1lb3V0IHBhdGggYW5kCmEgc3Vi c2VxdWVudCBjYWxsIHRvIHJlaW5pdF9jb21wbGV0aW9uKCZpMmMtPmRvbmUpIGluIGFtbF9pMmNf eGZlcl9tc2coKT8KCkluIGFtbF9pMmNfaXJxKCksIHRoZSBjb21wbGV0ZV9pcnFfb3V0IHBhdGgg c2V0cyBpMmMtPnN0YXRlID0gQTlfU1RBVEVfSURMRSwKcmVsZWFzZXMgaTJjLT5sb2NrIHZpYSBz cGluX3VubG9jaygmaTJjLT5sb2NrKSwgYW5kIHRoZW4gY2FsbHMKY29tcGxldGUoJmkyYy0+ZG9u ZSkgb3V0c2lkZSBpMmMtPmxvY2suIE1lYW53aGlsZSwgYW1sX2kyY194ZmVyX21zZygpCmluaXRp YWxpemVzIGkyYy0+bXNnLCBpMmMtPnBvcywgYW5kIGkyYy0+ZXJyb3IgYmVmb3JlIGFjcXVpcmlu ZyBpMmMtPmxvY2sgYW5kCmNhbGxpbmcgcmVpbml0X2NvbXBsZXRpb24oJmkyYy0+ZG9uZSkuCgpJ ZiBhIHRyYW5zZmVyIGZpbmlzaGVzIG9uIENQVSAxIGp1c3QgYXMgd2FpdF9mb3JfY29tcGxldGlv bl90aW1lb3V0KCkgZXhwaXJlcwpvbiBDUFUgMDoKCkNQVSAxIChhbWxfaTJjX2lycSkgICAgICAg ICAgICAgICAgQ1BVIDAgKGFtbF9pMmNfeGZlcl9tc2cpCi0tLS0tLS0tLS0tLS0tLS0tLS0gICAg ICAgICAgICAgICAgLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tCnNwaW5fdW5sb2NrKCZpMmMtPmxv Y2spOwogICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIC8qICF0aW1lX2xlZnQgdGlt ZW91dCBwYXRoICovCiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgc3Bpbl9sb2Nr X2lycXNhdmUoJmkyYy0+bG9jaywgZmxhZ3MpOwogICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIC4uLgogICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHNwaW5fdW5sb2Nr X2lycXJlc3RvcmUoJmkyYy0+bG9jaywgZmxhZ3MpOwogICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIHJldHVybiAtRVRJTUVET1VUOwoKICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAvKiBuZXh0IG1lc3NhZ2Ugc3RhcnRzICovCiAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgaTJjLT5tc2cgPSBtc2c7CiAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgc3Bpbl9sb2NrX2lycXNhdmUoJmkyYy0+bG9jaywgZmxhZ3MpOwogICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIGkyYy0+c3RhdGUgPSBBOV9TVEFURV9SRUFEOwogICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJlaW5pdF9jb21wbGV0aW9uKCZpMmMtPmRvbmUp OwogICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGFtbF9pMmNfZG9fc3RhcnQoaTJj LCBtc2cpOwogICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHNwaW5fdW5sb2NrX2ly cXJlc3RvcmUoJmkyYy0+bG9jaywgZmxhZ3MpOwogICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIHdhaXRfZm9yX2NvbXBsZXRpb25fdGltZW91dCgmaTJjLT5kb25lLCAuLi4pOwpjb21w bGV0ZSgmaTJjLT5kb25lKTsKCkluIHRoaXMgY2FzZSwgQ1BVIDEncyBkZWxheWVkIGNvbXBsZXRl KCZpMmMtPmRvbmUpIHdha2VzCndhaXRfZm9yX2NvbXBsZXRpb25fdGltZW91dCgpIGltbWVkaWF0 ZWx5IHdoaWxlIHRoZSBuZXcgdHJhbnNmZXIgaXMgc3RpbGwKYWN0aXZlIGluIGhhcmR3YXJlLiBU aGF0IGFsbG93cyBhbWxfaTJjX3hmZXJfbXNnKCkgdG8gcmV0dXJuIGVhcmx5IHdoaWxlCmFtbF9p MmNfaXJxKCkgY2FuIHN0aWxsIGFjY2VzcyBpMmMtPm1zZyBhbmQgd3JpdGUgdG8gaTJjLT5tc2ct PmJ1ZiBhZnRlciB0aGUKY2FsbGVyIGZyZWVzIG9yIHBvcHMgdGhlIGJ1ZmZlciwgb3Igd2hpbGUg dGhlIG5leHQgbWVzc2FnZSBpbiBhbWxfaTJjX3hmZXIoKQpvdmVyd3JpdGVzIGkyYy0+bXNnLCBp MmMtPnBvcywgYW5kIGkyYy0+ZXJyb3Igd2l0aG91dCBob2xkaW5nIGkyYy0+bG9jay4KClNob3Vs ZCBjb21wbGV0ZSgmaTJjLT5kb25lKSBiZSBjYWxsZWQgd2hpbGUgaG9sZGluZyBpMmMtPmxvY2ss IGFuZCBzaG91bGQKaTJjLT5tc2csIGkyYy0+cG9zLCBhbmQgaTJjLT5lcnJvciBiZSBhY2Nlc3Nl ZCB1bmRlciBpMmMtPmxvY2s/Cgo+ICsKPiArCWFtbF9pMmNfc2V0X21hc2soaTJjLCBSRUdfQ0ZH X0JVUywgQlVTX05PX1NUT1AsIChsYXN0ID8gMCA6IEJVU19OT19TVE9QKSk7Cj4gKwo+ICsJLyog U3RhcnQgdGhlIHRyYW5zZmVyICovCj4gKwlhbWxfaTJjX2RvX3N0YXJ0KGkyYywgbXNnKTsKPiAr CXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJmkyYy0+bG9jaywgZmxhZ3MpOwo+ICsKPiArCXRpbWVf bGVmdCA9IG1zZWNzX3RvX2ppZmZpZXMoSTJDX1RJTUVPVVRfTVMpOwo+ICsJdGltZV9sZWZ0ID0g d2FpdF9mb3JfY29tcGxldGlvbl90aW1lb3V0KCZpMmMtPmRvbmUsIHRpbWVfbGVmdCk7Cj4gKwo+ ICsJLyoKPiArCSAqIFByb3RlY3QgYWNjZXNzIHRvIGkyYyBzdHJ1Y3QgYW5kIHJlZ2lzdGVycyBm cm9tIGludGVycnVwdAo+ICsJICogaGFuZGxlcnMgdHJpZ2dlcmVkIGJ5IGEgdHJhbnNmZXIgdGVy bWluYXRlZCBhZnRlciB0aGUKPiArCSAqIHRpbWVvdXQgcGVyaW9kCj4gKwkgKi8KPiArCj4gKwlp ZiAoIXRpbWVfbGVmdCkgewo+ICsJCXNwaW5fbG9ja19pcnFzYXZlKCZpMmMtPmxvY2ssIGZsYWdz KTsKPiArCQlpMmMtPnN0YXRlID0gQTlfU1RBVEVfSURMRTsKPiArCQlhbWxfaTJjX3NldF9tYXNr KGkyYywgUkVHX0NGR19JUlFfRU5BQkxFLAo+ICsJCQkJIEE5X1JYX1RIUkVTSF9SRUFEIHwgQTlf VFhfVEhSRVNIX1dSSVRFLCAwKTsKPiArCQljbGVhcl9pcnFfc3RhdHVzKGkyYywgSVJRX0FMTF9N QVNLKTsKPiArCQlyZXNldF9maWZvX3BvcyhpMmMpOwo+ICsJCXNwaW5fdW5sb2NrX2lycXJlc3Rv cmUoJmkyYy0+bG9jaywgZmxhZ3MpOwo+ICsJCXJldHVybiAtRVRJTUVET1VUOwo+ICsJfQoKW1Nl dmVyaXR5OiBIaWdoXQpBcyByZXBvcnRlZCBieSBTYXNoaWtvIG9uIHYyIFszXSwgd2hlbiB3YWl0 X2Zvcl9jb21wbGV0aW9uX3RpbWVvdXQoKSBleHBpcmVzCmluIGFtbF9pMmNfeGZlcl9tc2coKSwg ZG9lcyB0aGUgdGltZW91dCBjbGVhbnVwIGxlYXZlIHRoZSBoYXJkd2FyZSB0cmFuc2ZlcgpydW5u aW5nIG9uIHRoZSBidXM/CgpJbiB0aGUgIXRpbWVfbGVmdCBibG9jaywgdGhlIGRyaXZlciByZXNl dHMgaTJjLT5zdGF0ZSA9IEE5X1NUQVRFX0lETEUsCmRpc2FibGVzIEE5X1JYX1RIUkVTSF9SRUFE IHwgQTlfVFhfVEhSRVNIX1dSSVRFIGluIFJFR19DRkdfSVJRX0VOQUJMRSwgY2xlYXJzClJFR19D RkdfSVJRX1NUQVRFLCBhbmQgY2FsbHMgcmVzZXRfZmlmb19wb3MoaTJjKSwgYnV0IGl0IG5ldmVy IGNsZWFycwpTVEFSVF9TVEFSVCBpbiBSRUdfQ0ZHX1NUQVJUIChvciBvdGhlcndpc2UgaGFsdHMg dGhlIGNvbnRyb2xsZXIpIHdoaWxlCkE5X0VOQUJMRV9JUlFfQklUIChBOV9OQ0tfRVJST1IgfCBB OV9QSFlfRE9ORSkgcmVtYWlucyBlbmFibGVkIGluClJFR19DRkdfSVJRX0VOQUJMRS4KCklmIGEg c3RhbGxlZCBidXMgdHJhbnNmZXIgY29udGludWVzIHNoaWZ0aW5nIGJ5dGVzIGFmdGVyIHJlc2V0 X2ZpZm9fcG9zKGkyYyksCml0IHdpbGwgYWR2YW5jZSB0aGUgaGFyZHdhcmUgRklGTyBwb2ludGVy cyBiZWZvcmUgdGhlIG5leHQgdHJhbnNmZXIgY2FsbHMKYW1sX2kyY19wcmVwYXJlX3hmZXIoKS4g RnVydGhlcm1vcmUsIGlmIHRoZSBzdGFsbGVkIHRyYW5zZmVyIGZpbmlzaGVzCihBOV9QSFlfRE9O RSkgb3IgTkFDS3MgKEE5X05DS19FUlJPUikgYWZ0ZXIgYSBzdWJzZXF1ZW50IGNhbGwgdG8KYW1s X2kyY194ZmVyX21zZygpIGhhcyBzZXQgaTJjLT5zdGF0ZSB0byBBOV9TVEFURV9SRUFEIG9yIEE5 X1NUQVRFX1dSSVRFIGFuZApyZWxlYXNlZCBpMmMtPmxvY2ssIGFtbF9pMmNfaXJxKCkgd2lsbCBz ZXJ2aWNlIHRoYXQgc3RhbGUgaW50ZXJydXB0IGFnYWluc3QKIHRoZSBuZXcgaTJjLT5tc2csIGNv cnJ1cHRpbmcgaTJjLT5tc2ctPmJ1ZiwgaTJjLT5wb3MsIGFuZCBpMmMtPmVycm9yIGFuZApwcmVt YXR1cmVseSBjb21wbGV0aW5nIGkyYy0+ZG9uZS4KClNob3VsZCB0aGUgdGltZW91dCBwYXRoIGNs ZWFyIFNUQVJUX1NUQVJUIGluIFJFR19DRkdfU1RBUlQgdG8gYWJvcnQgdGhlIGFjdGl2ZQpoYXJk d2FyZSB0cmFuc2ZlciB1bmRlciBpMmMtPmxvY2s/CgpbMV0gaHR0cHM6Ly9sb3JlLmtlcm5lbC5v cmcvci9zYXNoaWtvLW91dGJveC0xODEyODRAa2VybmVsLm9yZwpbMl0gaHR0cHM6Ly9sb3JlLmtl cm5lbC5vcmcvci9zYXNoaWtvLW91dGJveC0xODEyODRAa2VybmVsLm9yZwpbM10gaHR0cHM6Ly9s b3JlLmtlcm5lbC5vcmcvci9zYXNoaWtvLW91dGJveC0xODEyODRAa2VybmVsLm9yZwoKLS0gClNh c2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2FzaGlrby5kZXYvIy9wYXRjaHNldC8yMDI2MTEw NC1hOS1pMmMtdjctMC1iMzFmMmI1M2ZhZjRAYW1sb2dpYy5jb20/cGFydD0yCgpfX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hbWxvZ2ljIG1haWxp bmcgbGlzdApsaW51eC1hbWxvZ2ljQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmlu ZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hbWxvZ2ljCg==