From: sashiko-bot@kernel.org
To: "Jennifer Chan" <jenniferchan@meta.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: Add d3cold delay quirk for NVIDIA LR10 NVSwitch
Date: Thu, 05 Nov 2026 21:06:41 +0000 [thread overview]
Message-ID: <sashiko-outbox-200186@kernel.org> (raw)
In-Reply-To: <20261105201010.2297078-1-jenniferchan@meta.com>
> On a Supermicro HGX A100 system (X12DGO-6), each of the six LR10
> NVSwitches (10de:1af1) sits alone behind a PLX PEX 8725 (10b5:8725)
> downstream port. "nvidia-smi -r" resets all GPUs: NVML unbinds the
> switches from the nvidia-nvswitch driver, resets each one through sysfs
> (reset_method "bus", a Secondary Bus Reset of its port) and binds them
> again. The PCI core waits 100 ms after the link comes back, the switch
> answers config reads and the reset completes. When nvidia-nvswitch then
> probes the switches, one fails in pci_enable_device() with
>
> Unable to change power state from D3cold to D0, device inaccessible
>
> four others fail to initialize with -EIO, and the NVSwitch fabric does
> not come back.
>
> The same systems recover every time on a kernel that sleeps 1 s after
> [ ... ]
> up the hierarchy keep the default delay.
>
> Fixes: ac91e6980563 ("PCI: Unify delay handling for reset and resume")
> Cc: stable@vger.kernel.org
> Signed-off-by: Jennifer Chan <jenniferchan@meta.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261105201010.2297078-1-jenniferchan@meta.com?part=1
next prev parent reply other threads:[~2026-11-05 21:06 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-05 20:10 [PATCH] PCI: Add d3cold delay quirk for NVIDIA LR10 NVSwitch Jennifer Chan
2026-11-05 21:06 ` sashiko-bot [this message]
2026-11-05 21:51 ` Bjorn Helgaas
2026-11-05 23:21 ` Jennifer Chan
2026-11-06 10:57 ` Lukas Wunner
2026-11-06 17:43 ` Jason Gunthorpe
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