Re: [PATCH v3 3/3] arm64: dts: qcom: kodiak: add CSI2 D-PHY common-phy providers

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: kodiak: undocumented qcom,sc7280-csi2-phy compatible
- [Medium] arm64: dts: qcom: kodiak: single power-domain on csiphy0..4 breaks probe
- [Low] arm64: dts: qcom: kodiak: csiphy0..4 placed out of unit-address order
--

commit 052b5f2483e5e0bfe39a886df72e88b30b2413ff
Author: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>

arm64: dts: qcom: kodiak: add CSI2 D-PHY common-phy providers

This commit adds five standalone CSI2 D-PHY generic-PHY provider nodes
(csiphy0 through csiphy4) and their operating points table to kodiak.dtsi
for SC7280.

> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> index 8c7523602d271..e0e1fef7882ec 100644
> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi

[ ... ]

> @@ -5164,6 +5176,166 @@ cci1_i2c1: i2c-bus@1 {
>  			};
>  		};
>  
> +		csiphy0: phy@ace0000 {
> +			compatible = "qcom,sc7280-csi2-phy";

[Severity: Medium]
As reported by Sashiko on v2 [1], is the qcom,sc7280-csi2-phy compatible
string used on csiphy0 through csiphy4 documented in the Devicetree
bindings or supported by a driver in the tree?

In Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml,
only qcom,x1e80100-csi2-phy and qcom,glymur-csi2-phy are listed:

  compatible:
    oneOf:
      - const: qcom,x1e80100-csi2-phy
      - items:
          - const: qcom,glymur-csi2-phy
          - const: qcom,x1e80100-csi2-phy

Likewise, phy_qcom_mipi_csi2_of_match_table in
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c only matches
qcom,x1e80100-csi2-phy:

static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = {
	{ .compatible	= "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e },
	{ }
};

When a board or overlay enables one of csiphy0 through csiphy4 and connects
a sensor through it, camss_detect_legacy_phy() selects the non-legacy PHY
path and camss_init_subdevices() -> msm_csiphy_subdev_init() calls
devm_phy_get_by_of_node():

	csiphy->phy = devm_phy_get_by_of_node(dev, remote);
	of_node_put(remote);
	if (IS_ERR(csiphy->phy)) {
		ret = PTR_ERR(csiphy->phy);
		goto done;
	}

Without a matching PHY driver registered for qcom,sc7280-csi2-phy, will
dtbs_check fail validation and msm_csiphy_subdev_init() return
-EPROBE_DEFER indefinitely?

> +			reg = <0x0 0x0ace0000 0x0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
> +				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
> +			clock-names = "core",
> +				      "timer";
> +
> +			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
> +
> +			operating-points-v2 = <&csiphy_opp_table>;
> +
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +			power-domain-names = "top";

[Severity: Medium]
As reported by Sashiko on v2 [2], will specifying a single entry in
power-domains on csiphy0 through csiphy4 cause probing with the Qualcomm
MIPI CSI2 PHY driver to fail with -EEXIST?

When a platform device has a single power-domains entry,
platform_probe() -> dev_pm_domain_attach() -> genpd_dev_pm_attach()
attaches that domain directly to dev->pm_domain before invoking the
driver's probe callback:

	if (of_count_phandle_with_args(dev->of_node, "power-domains",
				       "#power-domain-cells") != 1)
		return 0;

	return __genpd_dev_pm_attach(dev, dev, 0, 1, true);

Subsequently, phy_qcom_mipi_csi2_probe() calls
phy_qcom_mipi_csi2_attach_pm_domains() -> devm_pm_domain_attach_list() ->
dev_pm_domain_attach_list(), which rejects devices that already have
dev->pm_domain populated:

	if (dev->pm_domain)
		return -EEXIST;

In addition, shouldn't csiphy0 through csiphy4 and csiphy_opp_table also
specify the RPMHPD voltage rail power domains and required-opps needed for
scaling between the 300 MHz and 400 MHz OPPs in
phy_qcom_mipi_csi2_set_clock_rates()?

[ ... ]

> +		csiphy4: phy@ace8000 {
> +			compatible = "qcom,sc7280-csi2-phy";
> +			reg = <0x0 0x0ace8000 0x0 0x2000>;

[ ... ]

> +		};
> +
>  		camss: isp@acb3000 {
>  			compatible = "qcom,sc7280-camss";

[Severity: Low]
As reported by Sashiko on v2 [3], this isn't a bug, but csiphy0 through
csiphy4 (phy@ace0000 through phy@ace8000) are placed before
camss: isp@acb3000 even though 0xace0000 is higher than 0xacb3000. Should
phy@ace0000 through phy@ace8000 be placed after isp@acb3000 (and before
camcc: clock-controller@ad00000) to keep the child nodes of soc@0 sorted
by unit address?

Also, the commit message states that csiphy_opp_table "moves to the root
node" and that its entries "are both kept unchanged", which describes
changes between patch revisions rather than against the baseline tree.

[1] https://lore.kernel.org/r/20261103221026.3662383-4-anusha.nandi@oss.qualcomm.com
[2] https://lore.kernel.org/r/20261103221026.3662383-4-anusha.nandi@oss.qualcomm.com
[3] https://lore.kernel.org/r/20261103221026.3662383-4-anusha.nandi@oss.qualcomm.com

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261106030212.2811027-1-anusha.nandi@oss.qualcomm.com?part=3