From: sashiko-bot@kernel.org
To: tze.yee.ng@altera.com, devicetree@vger.kernel.org
Cc: robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 2/4] mmc: sdhci-cadence6: program PHONY_DQS_TIMING for extended-read DDR
Date: Fri, 06 Nov 2026 06:22:57 +0000 [thread overview]
Message-ID: <sashiko-outbox-200889@kernel.org> (raw)
In-Reply-To: <20261106-sd_cadence_ddr50_v3-v3-2-cb50afece614@altera.com>
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] mmc: sdhci-cadence6: missing Fixes trailer for commit
882fb340a956
--
commit a251f955cff38a0f481d2f8c32d309cec95d2889
Author: Tze Yee Ng <tze.yee.ng@altera.com>
> mmc: sdhci-cadence6: program PHONY_DQS_TIMING for extended-read DDR
>
> The SD6HC PHY left PHONY_DQS_TIMING (phy_ctrl_reg[9:4]) at 0 in all
> modes. Per the Cadence DLL PHY documentation it must be the rebar (RE#)
> pulse width in clk_phy cycles minus 1 in extended read mode, and 0
> otherwise. Leaving it 0 in extended-read DDR duplicates one DDR edge
> (the silent odd/even edge-capture defect).
>
> On this integration the rebar pulse is 2 clk_phy cycles, so extended-
> read DDR needs 1; confirmed on DDR50 hardware (1 captures both beats, 2
> corrupts reads). Derive it from the extended-read-mode state and apply
> it only in DDR modes, since SDR extended-read samples a single edge and
> is unaffected.
>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
[Severity: Low]
Since this fixes a hardware programming defect in extended-read DDR modes
introduced when SD6HC support was added, should this include:
Fixes: 882fb340a956 ("mmc: sdhci-cadence: add Cadence SD6HC support")
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261106-sd_cadence_ddr50_v3-v3-0-cb50afece614@altera.com?part=2
next prev parent reply other threads:[~2026-11-06 6:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-06 6:16 [PATCH v3 0/4] mmc: sdhci-cadence: SD6HC DDR50/DDR52 read-path tuning and fixes tze.yee.ng
2026-11-06 6:16 ` [PATCH v3 1/4] mmc: sdhci-cadence: abort failed tuning command on SD6HC tze.yee.ng
2026-11-06 6:16 ` [PATCH v3 2/4] mmc: sdhci-cadence6: program PHONY_DQS_TIMING for extended-read DDR tze.yee.ng
2026-11-06 6:22 ` sashiko-bot [this message]
2026-11-06 6:16 ` [PATCH v3 3/4] dt-bindings: mmc: cdns,sd6hc: add SD6HC DDR50 read-path tuning tze.yee.ng
2026-11-06 12:40 ` Krzysztof Kozlowski
2026-11-06 6:16 ` [PATCH v3 4/4] mmc: sdhci-cadence6: read SD6HC DDR50 tuning from device tree tze.yee.ng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=sashiko-outbox-200889@kernel.org \
--to=sashiko-bot@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
--cc=tze.yee.ng@altera.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.