From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793955080; b=wUWjFani3cLXoGfdKIYqAkIMcVJD6/15ey+X3HDwIP5smwSezPTaw0Ad6bU08UP7i3vP qTmNmTVlL2sn/4yG5eNp6Ea1rkkTNfziegbbAH4RANnlyO7vR8ExcY0l7wsYCQgw09DGl ogAjWQIqDys4tPcypb2Gb97A6GPK2KLahgc1oDMfI5tx3zGug4dkRwGYy5F0DXJhEBOa9 RD+667TdRw799Vsz7s6xT+fIKKmlD/e14oJfr4kBH6hrTxJd5SKkTTlyD0wdhTuD1XBqK XpkQUSW7xWo/UTuZTCIBTtGQ8mtQujeB1ZWw8AOYKWrdZLKCtv1vSEuE8uYi/93RCKw== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793955080; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=ZPrMxi71NV9gjGGF2lBGP+8nq9DMZ0NgKsrzGDmzMVo=; b=3m8lQ1FVHveoRo5ygfItiUmZJd16aTQhcrUOBVPfy6sqL22l+nFBBiQAuhYruJB8QX4P +oo3djCtOvF8D8fb6/lp7wSjqFxn//rhP/mPXKBeOM4s2cIdbX3KDHhxSU8Ccb38cnzoh FWBkPtm9TmDN0wYlt0s7Gm9LvXicRnVmhSZE68ZL6BE4lrQ0+g7RqW1PhI8m7Azbd4QBw upYB9OGSUkb4swpdJp0VLIPUCX/GatcLUzKW5gx7gFC/aBD4eYP9GLTSw+gwrJX50xwsz qkcMoZq/ITWJ9pYcX+TqjAr2zcUPT39OZkIjuPQTT3R/uL5uZf4TiX3t7qsDkjDwNMg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=lfsoaVgX; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7648A606A329; Fri, 6 Nov 2026 08:51:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=lfsoaVgX Received: by smtp.kernel.org (Postfix) with ESMTPSA id 004E11F0089F; Fri, 6 Nov 2026 08:51:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793955080; bh=ZPrMxi71NV9gjGGF2lBGP+8nq9DMZ0NgKsrzGDmzMVo=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=lfsoaVgXm+zjdv8bk+icyZunADPHDj9zgn/y/eBZBkqG+CbludKkCD+kbdiKfzkWJ thHjsfR3WXEJgAmps0KhQ6k8u8ldnwkLWaI/A3kd0JFldwVXiPA+6JmZhSgvker/82 j9/Wg0sC5xMLnvUyuX0hkNACLlei75o8lBXylWo073UCwqPMV9Hwo7VgNXyeeTsjxU WqHufSzNdv09ALHlSGt0ZUG/hxKOMJybt78MxZpZddj7hlKi3YEjihxl/u6AXcI858 gXaVm8+7PBRsQfD1DpmnmxZbzBE/e18R7qJnc1ba9MqGub/MK200ChaKO6lOL07MhQ Ua2JxCqWZsjGA== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH 5/7] clk: amlogic: Add S7 PLL clock controller driver Reply-To: sashiko-reviews@lists.linux.dev To: "Carlo Caione" Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org In-Reply-To: <20261106-upstream-s7-clk-v1-5-7d501d62621f@baylibre.com> References: <20261106-upstream-s7-clk-v1-0-7d501d62621f@baylibre.com> <20261106-upstream-s7-clk-v1-5-7d501d62621f@baylibre.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Fri, 06 Nov 2026 08:51:19 +0000 X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [Medium] clk: meson: s7-pll: HDMIPLL_CTRL1 initialized after s7_hdmi_pll_div0p5 rate -- commit 6a51c26cbe37d4a7e3b2407e903405378e1e348b Author: Carlo Caione clk: amlogic: Add S7 PLL clock controller driver This commit adds the PLL clock controller driver for the Amlogic S7 SoC, providing the fixed PLL and its dividers, the GP0, HIFI0 and HIFI1 PLLs, and the HDMI PLL. > diff --git a/drivers/clk/meson/s7-pll.c b/drivers/clk/meson/s7-pll.c > new file mode 100644 > index 0000000000000..2aa253a5f2111 > --- /dev/null > +++ b/drivers/clk/meson/s7-pll.c [ ... ] > +static const struct reg_sequence s7_hdmi_pll_init_regs[] =3D { > + { .reg =3D HDMIPLL_CTRL0, .def =3D 0x00881000 }, > + { .reg =3D HDMIPLL_CTRL1, .def =3D 0x2c6011cc }, > + { .reg =3D HDMIPLL_CTRL2, .def =3D 0x86801000 }, > + { .reg =3D HDMIPLL_CTRL3, .def =3D 0x00000000 }, > +}; > + > +static const struct clk_div_table s7_hdmi_pll_div0p5_table[] =3D { > + { .val =3D 0, .div =3D 1 }, > + { .val =3D 1, .div =3D 2 }, > + { /* sentinel */ } > +}; > + > +static struct clk_regmap s7_hdmi_pll_div0p5 =3D { > + .data =3D &(struct clk_regmap_div_data) { > + .offset =3D HDMIPLL_CTRL1, > + .shift =3D 19, > + .width =3D 1, > + .table =3D s7_hdmi_pll_div0p5_table, > + .flags =3D CLK_DIVIDER_READ_ONLY, > + }, > + .hw.init =3D &(struct clk_init_data) { > + .name =3D "hdmi_pll_div0p5", > + .ops =3D &clk_regmap_divider_ro_ops, > + .parent_data =3D &(const struct clk_parent_data) { > + .fw_name =3D "hdmi", > + }, > + .num_parents =3D 1, > + }, > +}; > + > +static struct clk_regmap s7_hdmi_pll_vco =3D { > + .data =3D &(struct meson_clk_pll_data) { > + .en =3D { > + .reg_off =3D HDMIPLL_CTRL0, > + .shift =3D 28, > + .width =3D 1, > + }, > + .m =3D { > + .reg_off =3D HDMIPLL_CTRL0, > + .shift =3D 0, > + .width =3D 9, > + }, > + .frac =3D { > + .reg_off =3D HDMIPLL_CTRL3, > + .shift =3D 0, > + .width =3D 17, > + }, > + .l =3D { > + .reg_off =3D HDMIPLL_STS, > + .shift =3D 31, > + .width =3D 1, > + }, > + .rst =3D { > + .reg_off =3D HDMIPLL_CTRL0, > + .shift =3D 29, > + .width =3D 1, > + }, > + .range =3D &s7_hdmi_pll_mult_range, > + .init_regs =3D s7_hdmi_pll_init_regs, > + .init_count =3D ARRAY_SIZE(s7_hdmi_pll_init_regs), > + .flags =3D CLK_MESON_PLL_RST_ACTIVE_LOW | > + CLK_MESON_PLL_NOINIT_ENABLED, > + }, > + .hw.init =3D &(struct clk_init_data) { > + .name =3D "hdmi_pll_vco", > + .ops =3D &meson_clk_pll_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &s7_hdmi_pll_div0p5.hw > + }, > + .num_parents =3D 1, > + }, > +}; [ ... ] > +static struct clk_hw *s7_pll_hws[] =3D { [ ... ] > + [CLKID_HDMI_PLL_DIV0P5] =3D &s7_hdmi_pll_div0p5.hw, > + [CLKID_HDMI_PLL_VCO] =3D &s7_hdmi_pll_vco.hw, [Severity: Medium] Can s7_hdmi_pll_div0p5 cache a stale divide-by-2 rate before s7_hdmi_pll_vco initializes HDMIPLL_CTRL1? meson_clkc_init() registers s7_pll_hws[] in index order, so s7_hdmi_pll_div0p5 reads HDMIPLL_CTRL1 bit 19 and caches its rate before s7_hdmi_pll_vco runs meson_clk_pll_init() and writes s7_hdmi_pll_init_regs (which clears HDMIPLL_CTRL1 bit 19 to 0 when the PLL is not already enabled by firmware). Because s7_hdmi_pll_div0p5 uses clk_regmap_divider_ro_ops without CLK_GET_RATE_NOCACHE, its cached rate is never updated after HDMIPLL_CTRL1 is overwritten, which would leave s7_hdmi_pll_vco and all downstream HDMI PLL clocks calculating rates off by a factor of 2 if bit 19 was set prior to initialization. --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261106-upstream-s= 7-clk-v1-0-7d501d62621f@baylibre.com?part=3D5 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8566D606A32C for ; Fri, 6 Nov 2026 08:51:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=uCzgPSf/; dkim=fail reason="signature verification failed" (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=lfsoaVgX DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Date:References: In-Reply-To:Cc:To:Subject:From:Message-ID:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Unsubscribe-Post:List-Owner; bh=lGf/hj+pNCrnmhYtdKl3IZnbpfP6G7uG5IFunp/mFHw=; b=uCzgPSf/xgIOK61GqkhBVo4ASm RyTmt6rSPbikaVZmRypxDa4N24BHV6jpyfo+3N8p5NTzrJ0Py6vAIkrSAX+Tuntoo+jHYRyrkDr1N XxUqDPrHBR/mVFO8950hnuUSPNGj25JFaSwGJYE8xmMZ5o3zOuE7nyvQqqdRw3eci+XjPSyAUZyru eGt7QpI4LPi7ZVtGrTPND7JhSl/oAOL8IIEhHXY5xxBbLZ7Vwt5oR2EaleCu7eBxSYWdlttM+aYX5 dn8InvtYomJGOXosAVdzOxOeoQT3thlABBIzg2Ka1pSGU/rMOQ3Xu3A1xttRFzK7bt1ucpBkPvGic y6gS5kdA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xPFfP-0000000BdO5-1UiA; Fri, 06 Nov 2026 08:51:23 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xPFfN-0000000BdNG-1pfN for linux-amlogic@lists.infradead.org; Fri, 06 Nov 2026 08:51:21 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 98CFB601BF; Fri, 6 Nov 2026 08:51:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 004E11F0089F; Fri, 6 Nov 2026 08:51:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793955080; bh=ZPrMxi71NV9gjGGF2lBGP+8nq9DMZ0NgKsrzGDmzMVo=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=lfsoaVgXm+zjdv8bk+icyZunADPHDj9zgn/y/eBZBkqG+CbludKkCD+kbdiKfzkWJ thHjsfR3WXEJgAmps0KhQ6k8u8ldnwkLWaI/A3kd0JFldwVXiPA+6JmZhSgvker/82 j9/Wg0sC5xMLnvUyuX0hkNACLlei75o8lBXylWo073UCwqPMV9Hwo7VgNXyeeTsjxU WqHufSzNdv09ALHlSGt0ZUG/hxKOMJybt78MxZpZddj7hlKi3YEjihxl/u6AXcI858 gXaVm8+7PBRsQfD1DpmnmxZbzBE/e18R7qJnc1ba9MqGub/MK200ChaKO6lOL07MhQ Ua2JxCqWZsjGA== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH 5/7] clk: amlogic: Add S7 PLL clock controller driver To: "Carlo Caione" Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org In-Reply-To: <20261106-upstream-s7-clk-v1-5-7d501d62621f@baylibre.com> References: <20261106-upstream-s7-clk-v1-0-7d501d62621f@baylibre.com> <20261106-upstream-s7-clk-v1-5-7d501d62621f@baylibre.com> Date: Fri, 06 Nov 2026 08:51:19 +0000 X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-amlogic" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MSBwb3RlbnRpYWwKaXNzdWUgdG8gY29uc2lkZXI6Ci0gW01lZGl1bV0gY2xrOiBtZXNvbjogczct cGxsOiBIRE1JUExMX0NUUkwxIGluaXRpYWxpemVkIGFmdGVyCiAgczdfaGRtaV9wbGxfZGl2MHA1 IHJhdGUKLS0KCmNvbW1pdCA2YTUxYzI2Y2JlMzdkNGE3ZTNiMjQwN2U5MDM0MDUzNzhlMWUzNDhi CkF1dGhvcjogQ2FybG8gQ2Fpb25lIDxjY2Fpb25lQGJheWxpYnJlLmNvbT4KCmNsazogYW1sb2dp YzogQWRkIFM3IFBMTCBjbG9jayBjb250cm9sbGVyIGRyaXZlcgoKVGhpcyBjb21taXQgYWRkcyB0 aGUgUExMIGNsb2NrIGNvbnRyb2xsZXIgZHJpdmVyIGZvciB0aGUgQW1sb2dpYyBTNyBTb0MsCnBy b3ZpZGluZyB0aGUgZml4ZWQgUExMIGFuZCBpdHMgZGl2aWRlcnMsIHRoZSBHUDAsIEhJRkkwIGFu ZCBISUZJMSBQTExzLAphbmQgdGhlIEhETUkgUExMLgoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9j bGsvbWVzb24vczctcGxsLmMgYi9kcml2ZXJzL2Nsay9tZXNvbi9zNy1wbGwuYwo+IG5ldyBmaWxl IG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMDAwMDAwMC4uMmFhMjUzYTVmMjExMQo+IC0tLSAv ZGV2L251bGwKPiArKysgYi9kcml2ZXJzL2Nsay9tZXNvbi9zNy1wbGwuYwoKWyAuLi4gXQoKPiAr c3RhdGljIGNvbnN0IHN0cnVjdCByZWdfc2VxdWVuY2UgczdfaGRtaV9wbGxfaW5pdF9yZWdzW10g PSB7Cj4gKwl7IC5yZWcgPSBIRE1JUExMX0NUUkwwLAkuZGVmID0gMHgwMDg4MTAwMCB9LAo+ICsJ eyAucmVnID0gSERNSVBMTF9DVFJMMSwJLmRlZiA9IDB4MmM2MDExY2MgfSwKPiArCXsgLnJlZyA9 IEhETUlQTExfQ1RSTDIsCS5kZWYgPSAweDg2ODAxMDAwIH0sCj4gKwl7IC5yZWcgPSBIRE1JUExM X0NUUkwzLAkuZGVmID0gMHgwMDAwMDAwMCB9LAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0 cnVjdCBjbGtfZGl2X3RhYmxlIHM3X2hkbWlfcGxsX2RpdjBwNV90YWJsZVtdID0gewo+ICsJeyAu dmFsID0gMCwgLmRpdiA9IDEgfSwKPiArCXsgLnZhbCA9IDEsIC5kaXYgPSAyIH0sCj4gKwl7IC8q IHNlbnRpbmVsICovIH0KPiArfTsKPiArCj4gK3N0YXRpYyBzdHJ1Y3QgY2xrX3JlZ21hcCBzN19o ZG1pX3BsbF9kaXYwcDUgPSB7Cj4gKwkuZGF0YSA9ICYoc3RydWN0IGNsa19yZWdtYXBfZGl2X2Rh dGEpIHsKPiArCQkub2Zmc2V0ID0gSERNSVBMTF9DVFJMMSwKPiArCQkuc2hpZnQgPSAxOSwKPiAr CQkud2lkdGggPSAxLAo+ICsJCS50YWJsZSA9IHM3X2hkbWlfcGxsX2RpdjBwNV90YWJsZSwKPiAr CQkuZmxhZ3MgPSBDTEtfRElWSURFUl9SRUFEX09OTFksCj4gKwl9LAo+ICsJLmh3LmluaXQgPSAm KHN0cnVjdCBjbGtfaW5pdF9kYXRhKSB7Cj4gKwkJLm5hbWUgPSAiaGRtaV9wbGxfZGl2MHA1IiwK PiArCQkub3BzID0gJmNsa19yZWdtYXBfZGl2aWRlcl9yb19vcHMsCj4gKwkJLnBhcmVudF9kYXRh ID0gJihjb25zdCBzdHJ1Y3QgY2xrX3BhcmVudF9kYXRhKSB7Cj4gKwkJCS5md19uYW1lID0gImhk bWkiLAo+ICsJCX0sCj4gKwkJLm51bV9wYXJlbnRzID0gMSwKPiArCX0sCj4gK307Cj4gKwo+ICtz dGF0aWMgc3RydWN0IGNsa19yZWdtYXAgczdfaGRtaV9wbGxfdmNvID0gewo+ICsJLmRhdGEgPSAm KHN0cnVjdCBtZXNvbl9jbGtfcGxsX2RhdGEpIHsKPiArCQkuZW4gPSB7Cj4gKwkJCS5yZWdfb2Zm ID0gSERNSVBMTF9DVFJMMCwKPiArCQkJLnNoaWZ0ICAgPSAyOCwKPiArCQkJLndpZHRoICAgPSAx LAo+ICsJCX0sCj4gKwkJLm0gPSB7Cj4gKwkJCS5yZWdfb2ZmID0gSERNSVBMTF9DVFJMMCwKPiAr CQkJLnNoaWZ0ICAgPSAwLAo+ICsJCQkud2lkdGggICA9IDksCj4gKwkJfSwKPiArCQkuZnJhYyA9 IHsKPiArCQkJLnJlZ19vZmYgPSBIRE1JUExMX0NUUkwzLAo+ICsJCQkuc2hpZnQgICA9IDAsCj4g KwkJCS53aWR0aCAgID0gMTcsCj4gKwkJfSwKPiArCQkubCA9IHsKPiArCQkJLnJlZ19vZmYgPSBI RE1JUExMX1NUUywKPiArCQkJLnNoaWZ0ICAgPSAzMSwKPiArCQkJLndpZHRoICAgPSAxLAo+ICsJ CX0sCj4gKwkJLnJzdCA9IHsKPiArCQkJLnJlZ19vZmYgPSBIRE1JUExMX0NUUkwwLAo+ICsJCQku c2hpZnQgICA9IDI5LAo+ICsJCQkud2lkdGggICA9IDEsCj4gKwkJfSwKPiArCQkucmFuZ2UgPSAm czdfaGRtaV9wbGxfbXVsdF9yYW5nZSwKPiArCQkuaW5pdF9yZWdzID0gczdfaGRtaV9wbGxfaW5p dF9yZWdzLAo+ICsJCS5pbml0X2NvdW50ID0gQVJSQVlfU0laRShzN19oZG1pX3BsbF9pbml0X3Jl Z3MpLAo+ICsJCS5mbGFncyA9IENMS19NRVNPTl9QTExfUlNUX0FDVElWRV9MT1cgfAo+ICsJCQkg Q0xLX01FU09OX1BMTF9OT0lOSVRfRU5BQkxFRCwKPiArCX0sCj4gKwkuaHcuaW5pdCA9ICYoc3Ry dWN0IGNsa19pbml0X2RhdGEpIHsKPiArCQkubmFtZSA9ICJoZG1pX3BsbF92Y28iLAo+ICsJCS5v cHMgPSAmbWVzb25fY2xrX3BsbF9vcHMsCj4gKwkJLnBhcmVudF9od3MgPSAoY29uc3Qgc3RydWN0 IGNsa19odyAqW10pIHsKPiArCQkJJnM3X2hkbWlfcGxsX2RpdjBwNS5odwo+ICsJCX0sCj4gKwkJ Lm51bV9wYXJlbnRzID0gMSwKPiArCX0sCj4gK307CgpbIC4uLiBdCgo+ICtzdGF0aWMgc3RydWN0 IGNsa19odyAqczdfcGxsX2h3c1tdID0gewoKWyAuLi4gXQoKPiArCVtDTEtJRF9IRE1JX1BMTF9E SVYwUDVdCQk9ICZzN19oZG1pX3BsbF9kaXYwcDUuaHcsCj4gKwlbQ0xLSURfSERNSV9QTExfVkNP XQkJPSAmczdfaGRtaV9wbGxfdmNvLmh3LAoKW1NldmVyaXR5OiBNZWRpdW1dCkNhbiBzN19oZG1p X3BsbF9kaXYwcDUgY2FjaGUgYSBzdGFsZSBkaXZpZGUtYnktMiByYXRlIGJlZm9yZQpzN19oZG1p X3BsbF92Y28gaW5pdGlhbGl6ZXMgSERNSVBMTF9DVFJMMT8KCm1lc29uX2Nsa2NfaW5pdCgpIHJl Z2lzdGVycyBzN19wbGxfaHdzW10gaW4gaW5kZXggb3JkZXIsIHNvCnM3X2hkbWlfcGxsX2RpdjBw NSByZWFkcyBIRE1JUExMX0NUUkwxIGJpdCAxOSBhbmQgY2FjaGVzIGl0cyByYXRlIGJlZm9yZQpz N19oZG1pX3BsbF92Y28gcnVucyBtZXNvbl9jbGtfcGxsX2luaXQoKSBhbmQgd3JpdGVzCnM3X2hk bWlfcGxsX2luaXRfcmVncyAod2hpY2ggY2xlYXJzIEhETUlQTExfQ1RSTDEgYml0IDE5IHRvIDAg d2hlbiB0aGUKUExMIGlzIG5vdCBhbHJlYWR5IGVuYWJsZWQgYnkgZmlybXdhcmUpLiBCZWNhdXNl IHM3X2hkbWlfcGxsX2RpdjBwNSB1c2VzCmNsa19yZWdtYXBfZGl2aWRlcl9yb19vcHMgd2l0aG91 dCBDTEtfR0VUX1JBVEVfTk9DQUNIRSwgaXRzIGNhY2hlZCByYXRlCmlzIG5ldmVyIHVwZGF0ZWQg YWZ0ZXIgSERNSVBMTF9DVFJMMSBpcyBvdmVyd3JpdHRlbiwgd2hpY2ggd291bGQgbGVhdmUKczdf aGRtaV9wbGxfdmNvIGFuZCBhbGwgZG93bnN0cmVhbSBIRE1JIFBMTCBjbG9ja3MgY2FsY3VsYXRp bmcgcmF0ZXMgb2ZmCmJ5IGEgZmFjdG9yIG9mIDIgaWYgYml0IDE5IHdhcyBzZXQgcHJpb3IgdG8g aW5pdGlhbGl6YXRpb24uCgotLSAKU2FzaGlrbyBBSSByZXZpZXcgwrcgaHR0cHM6Ly9zYXNoaWtv LmRldi8jL3BhdGNoc2V0LzIwMjYxMTA2LXVwc3RyZWFtLXM3LWNsay12MS0wLTdkNTAxZDYyNjIx ZkBiYXlsaWJyZS5jb20/cGFydD01CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpsaW51eC1hbWxvZ2ljIG1haWxpbmcgbGlzdApsaW51eC1hbWxvZ2ljQGxp c3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0 aW5mby9saW51eC1hbWxvZ2ljCg==