Re: [PATCH v8 08/11] arm64: dts: qcom: ipq5210: Enable the PWM block

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] arm64: dts: qcom: ipq5210: pwm node enabled in SoC DTSI instead
  of board DTSI
--

commit 9b1049e040d5bbafe187118c25b0e6a3e6d556f6
Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>

arm64: dts: qcom: ipq5210: Enable the PWM block

This commit adds the PWM controller node to the IPQ5210 SoC device tree
and configures its pinmux on the RDP504 common board file.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi
> index 422e2766478a9..b32daa7c1559e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi
> @@ -89,6 +89,11 @@ &pcie1_port0 {
>  	reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
>  };
>  
> +&pwm {
> +	pinctrl-0 = <&pwm_default_state>;
> +	pinctrl-names = "default";
> +};
> +
>  &qpic_nand {
>  	pinctrl-0 = <&qpic_snand_default_state>;
>  	pinctrl-names = "default";

[ ... ]

> diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> index de3504395c48d..e4a696a65e550 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> @@ -406,6 +406,16 @@ tcsr: syscon@1937000 {
>  			reg = <0x0 0x01937000 0x0 0x2b000>;
>  		};
>  
> +		pwm: pwm@1941010 {
> +			compatible = "qcom,ipq5210-pwm", "qcom,ipq6018-pwm";
> +			reg = <0x0 0x01941010 0x0 0x20>;
> +			clocks = <&gcc GCC_ADSS_PWM_CLK>;
> +			assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
> +			assigned-clock-rates = <100000000>;
> +			#pwm-cells = <3>;
> +			status = "okay";
> +		};

[Severity: Low]
Should pwm@1941010 set status = "disabled" in ipq5210.dtsi and move
status = "okay" to &pwm in ipq5210-rdp504-common.dtsi?

Because the PWM output requires board-specific pinmux configuration and
other peripherals in ipq5210.dtsi (along with pwm@1941010 in sibling IPQ
SoC files) default to disabled, enabling it at the SoC level causes any
IPQ5210 board that does not use PWM to probe ipq_pwm_probe(), which calls
devm_clk_get_enabled() and devm_clk_rate_exclusive_get() and keeps
GCC_ADSS_PWM_CLK enabled and locked at 100 MHz without consumers.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261106-08-dts-v8-0-d91401955039@oss.qualcomm.com?part=8