Re: [PATCH 1/3] dt-bindings: clock: sun4i-a10-ccu: add Allwinner B288

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: clock: sun8i-b288-ccu: inconsistent clock and reset
  macro names
--

commit fb1a7b2f6dc03665d0714b13f4a0587e1bb34467
Author: Pablo Mazzini <pmazzini@gmail.com>

dt-bindings: clock: sun4i-a10-ccu: add Allwinner B288

This commit adds the Allwinner B288 CCU compatible string to the
sun4i-a10-ccu binding schema and introduces the clock and reset DT binding
headers for the SoC.

> diff --git a/include/dt-bindings/clock/sun8i-b288-ccu.h b/include/dt-bindings/clock/sun8i-b288-ccu.h
> new file mode 100644
> index 0000000000000..c9b9eaf979ad0
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun8i-b288-ccu.h
> @@ -0,0 +1,82 @@

[ ... ]

> +#define CLK_NAND	18
> +#define CLK_MMC0	19
> +#define CLK_MMC1	20
> +#define CLK_MMC2	21
> +#define CLK_MMC3	22
> +#define CLK_SPI0	23
> +#define CLK_SPI1	24
> +#define CLK_SPI2	25
> +#define CLK_DRAM	26

[ ... ]

> +#define CLK_BUS_THS	32
> +#define CLK_BUS_NAND	33
> +#define CLK_BUS_SDMMC0_BUS	34
> +#define CLK_BUS_SDMMC1_BUS	35
> +#define CLK_BUS_SDMMC2_BUS	36
> +#define CLK_BUS_SDMMC3_BUS	37

[ ... ]

> +#define CLK_BUS_USBOHCI0	46
> +#define CLK_BUS_USBEHCI0	47
> +#define CLK_BUS_USBOTG	48
> +#define CLK_BUS_DE	49
> +#define CLK_BUS_EE	50
> +#define CLK_BUS_TCON0	51
> +#define CLK_BUS_CSI	52
> +#define CLK_BUS_ADDA	53
> +#define CLK_BUS_SDRAM	54

[ ... ]

> +#define CLK_BUS_TWI0	63
> +#define CLK_BUS_TWI1	64
> +#define CLK_BUS_TWI2	65

[ ... ]

> diff --git a/include/dt-bindings/reset/sun8i-b288-ccu.h b/include/dt-bindings/reset/sun8i-b288-ccu.h
> new file mode 100644
> index 0000000000000..6751456545487
> --- /dev/null
> +++ b/include/dt-bindings/reset/sun8i-b288-ccu.h
> @@ -0,0 +1,45 @@

[ ... ]

> +#define RST_BUS_MMC0	2
> +#define RST_BUS_MMC1	3
> +#define RST_BUS_MMC2	4
> +#define RST_BUS_MMC3	5

[ ... ]

> +#define RST_USBPHY0	14
> +#define RST_BUS_OHCI0	15
> +#define RST_BUS_EHCI0	16
> +#define RST_BUS_OTG	17

[ ... ]

> +#define RST_BUS_DRAM	25

[ ... ]

> +#define RST_BUS_I2C0	34
> +#define RST_BUS_I2C1	35
> +#define RST_BUS_I2C2	36

[Severity: Low]
Could these macro names be aligned between the clock and reset headers and
with existing sunxi-ng CCU bindings before they become ABI?

Specifically:
- CLK_BUS_SDMMC0_BUS..CLK_BUS_SDMMC3_BUS vs. CLK_BUS_MMC0..CLK_BUS_MMC3
  (matching CLK_MMC0..3 and RST_BUS_MMC0..3, without the redundant _BUS
  suffix)
- CLK_BUS_USBOHCI0, CLK_BUS_USBEHCI0, and CLK_BUS_USBOTG vs.
  CLK_BUS_OHCI0, CLK_BUS_EHCI0, and CLK_BUS_OTG (matching RST_BUS_OHCI0,
  RST_BUS_EHCI0, and RST_BUS_OTG)
- CLK_BUS_SDRAM vs. CLK_BUS_DRAM (matching CLK_DRAM and RST_BUS_DRAM)
- CLK_BUS_TWI0..CLK_BUS_TWI2 vs. CLK_BUS_I2C0..CLK_BUS_I2C2 (matching
  RST_BUS_I2C0..2)
- RST_USBPHY0 vs. RST_USB_PHY0 (matching other Allwinner CCU reset headers)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108155702.361022-1-pmazzini@gmail.com?part=1