Re: [PATCH 2/5] dt-bindings: arm: stm32: Add clock-controller sub-node to STM32MP2 SYSCFG

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: arm: stm32: split STM32MP23/25 SYSCFG into separate
  schema
--

commit a55565d107267a4ad1a075c0905a54ac3317622d
Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

dt-bindings: arm: stm32: Add clock-controller sub-node to STM32MP2 SYSCFG

This commit adds a clock-controller sub-node to the STM32 SYSCFG binding,
requiring it on st,stm32mp23-syscfg and st,stm32mp25-syscfg and forbidding
it on all other variants.

> diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> index a559f8b03b842..38c844e8f19db 100644
> --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> @@ -45,6 +45,10 @@ properties:
>    "#size-cells":
>      const: 1
>  
> +  clock-controller:
> +    type: object
> +    $ref: /schemas/clock/st,stm32mp25-syscfg-clk.yaml#
> +
>  patternProperties:
>    "^phy@2[48]00$":
>      type: object
> @@ -80,6 +84,7 @@ allOf:
>          - "#address-cells"
>          - "#clock-cells"
>          - "#size-cells"
> +        - clock-controller
>          - phy@2400
>          - phy@2800
>      else:
> @@ -87,6 +92,7 @@ allOf:
>          '#address-cells': false
>          '#clock-cells': false
>          '#size-cells': false
> +        clock-controller: false
>          phy@2400: false
>          phy@2800: false

[Severity: Low]
Should st,stm32mp23-syscfg and st,stm32mp25-syscfg be split into a
separate binding schema?

Unlike the other seven compatibles in st,stm32-syscon.yaml, which only
take compatible, reg and optionally clocks, the STM32MP23/25 variants
forbid clocks and require six dedicated properties and sub-nodes
(#address-cells, #clock-cells, #size-cells, clock-controller, phy@2400
and phy@2800) that have to be explicitly set to false for every other SoC.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261110-ups_mp25_clk_syscfg-v1-0-667829cd290a@foss.st.com?part=2