Re: [PATCH v5 4/7] drm/xe/oa: Skip OA HW teardown on a wedged device

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] drm/xe/oa: build failure from non-existent xe_wedge.h and
  xe_wedged()
--

commit cfe215fb928c6338b6dd8582d19a4f894fb6bd7d
Author: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

drm/xe/oa: Skip OA HW teardown on a wedged device

This commit skips OA stream disabling and hardware teardown when destroying
an OA stream on a wedged device, and ensures the poll timer is unconditionally
canceled in xe_oa_stream_destroy().

> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index df9a3ea0875d1..6383a2e036ab0 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -43,6 +43,7 @@
>  #include "xe_sriov.h"
>  #include "xe_sync.h"
>  #include "xe_wa.h"
> +#include "xe_wedge.h"

[ ... ]

> @@ -905,7 +911,12 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
>  
>  	mutex_destroy(&stream->stream_lock);
>  
> -	xe_oa_stream_hw_teardown(stream);
> +	/* The poll timer may still be armed if the OA disable was skipped */
> +	hrtimer_cancel(&stream->poll_check_timer);
> +
> +	if (!xe_wedged(stream->oa->xe))
> +		xe_oa_stream_hw_teardown(stream);
> +
>  	xe_oa_free_oa_buffer(stream);
>  	xe_oa_stream_free_resources(stream);
>  }
> @@ -1704,7 +1715,8 @@ static void xe_oa_destroy_locked(struct xe_oa_stream *stream)
>  {
>  	xe_pm_runtime_get(gt_to_xe(stream->gt));
>  
> -	if (stream->enabled)
> +	/* A wedged device may be unresponsive, skip HW access */
> +	if (stream->enabled && !xe_wedged(gt_to_xe(stream->gt)))
>  		xe_oa_disable_locked(stream);

[Severity: High]
Does this break the build?  Neither xe_wedge.h nor xe_wedged() exists in the
tree.  The helper for checking whether an xe_device is wedged is
xe_device_wedged() in drivers/gpu/drm/xe/xe_device.h, which xe_oa.c already
includes.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261110190052.3514226-9-umesh.nerlige.ramappa@intel.com?part=4