From: sashiko-bot@kernel.org
To: "Zhu Jun" <zhujun2@cmss.chinamobile.com>
Cc: linux-rtc@vger.kernel.org,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>
Subject: Re: [PATCH] rtc: ac100: Program clock divider encodings without subtracting one
Date: Thu, 12 Nov 2026 07:20:08 +0000 [thread overview]
Message-ID: <sashiko-outbox-210588@kernel.org> (raw)
In-Reply-To: <20261112071620.154398-1-zhujun2@cmss.chinamobile.com>
> divider_get_val() already returns the hardware encoding for the
> power-of-two divider, and ac100_clkout_prediv[].val is also a register
> encoding. Subtracting one from either value programs the previous
> divider setting and turns encoding zero into all ones.
>
> For example, selecting a 32768 Hz output from the 32768 Hz parent
> programs divider seven and produces 256 Hz. Write both encodings
> directly so the programmed rate agrees with the requested rate.
>
> Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")
> Signed-off-by: Zhu Jun <zhujun2@cmss.chinamobile.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112071620.154398-1-zhujun2@cmss.chinamobile.com?part=1
prev parent reply other threads:[~2026-11-12 7:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-12 7:16 [PATCH] rtc: ac100: Program clock divider encodings without subtracting one Zhu Jun
2026-11-12 7:20 ` sashiko-bot [this message]
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