Re: [PATCH v2 1/2] usb: core: Pair ports of different hubs through their connector

[sashiko-bot@kernel.org]

> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> A USB 3 port is two ports to the USB core, a USB 2.0 one and a
> SuperSpeed one, and the core pairs them as peers. Root hub ports are
> paired with the same port number of the other root hub of the same
> xHCI, unless ACPI gives their locations.
> 
> Some SoCs route the two halves of a connector to different host
> controllers. On the Rockchip RK3588, USB 3.0 host 2 is SuperSpeed-only:
> its own USB 2.0 root hub port is not wired to a PHY, and the connector's
> USB 2.0 lines go to a separate EHCI instead. Default pairing then joins
> the SuperSpeed port to a dead USB 2.0 port, and nothing knows about the
> EHCI port that really shares the connector.
> 
> A usb-connector node describes its USB 2.0 data lines as graph port 0
> and its SuperSpeed lanes as graph port 1. When a hub's or host
> controller's graph links one of its ports to a connector whose other
> half leads to a different hub or host controller, pair the port with
> that one instead, and keep it out of the default pairing. Connectors
> whose two halves end on the same node, like a Type-C connector on a
> DWC3, keep the default pairing.
> 
> This lets the runtime PM rules for peers (keep the SuperSpeed port
> powered while its USB 2.0 peer is) apply to such connectors too.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>

Sashiko has reviewed this patch and found no issues.

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Sashiko AI review · https://sashiko.dev/#/patchset/20261112-usb-port-pairing-v2-0-45f5a1a29f1f@gmail.com?part=1