Re: [PATCH v2 2/2] arm64: dts: qcom: sm8150: Fix missing wake-gpios in PCI

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: sm8150: pcie1 wake-gpios uses
  GPIO_ACTIVE_HIGH polarity
--

commit 809c46a66ec46c6ef99060dec4a500e026dc122f
Author: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

arm64: dts: qcom: sm8150: Fix missing wake-gpios in PCI

This commit replaces the unused enable-gpio property on pcie1 with a
wake-gpios property in its pcie@0 root port node.

> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index b9846b424a938..d667e38914519 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -2028,8 +2028,6 @@ pcie1: pcie@1c08000 {
>  
>  			power-domains = <&gcc PCIE_1_GDSC>;
>  
> -			enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
> -
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&pcie1_default_state>;
>  
> @@ -2042,6 +2040,7 @@ pcie@0 {
>  
>  				phys = <&pcie1_phy>;
>  				reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
> +				wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;

[Severity: Medium]
Should wake-gpios use GPIO_ACTIVE_LOW here, matching pcie0 after commit
463d931d6a66 ("arm64: dts: qcom: sm8150: Fix PCIe WAKE# GPIO polarity")?

PCIe WAKE# is active-low and pcie1_default_state configures gpio104 with
bias-pull-up.  With GPIO_ACTIVE_HIGH, pci_configure_wake_irq() requests the
wake interrupt as IRQ_TYPE_LEVEL_HIGH, which triggers immediately while the
pulled-up WAKE# line is idle during suspend.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112120030.99510-3-krzysztof.kozlowski@oss.qualcomm.com?part=2