From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794549876; b=PbWAv4gDmR9hKVmtn0tAM9qqBvMxQu0EAdZpvJKpd8AtieGl2FRJwmW0Ajj8XFlVOxeS WN+sYG0La1tkAuhk6FlWoJxDimQWIbc3rZTaTLQr9LHivD+Spojy0+1F6vthcTJCKR9sX 8t7wck1C5kPBEMmtz0+cTsdNxx+cvvZwz5DwkM13bRqzY4nQl2uNxL8mfceWVC+3G0IZp 4usyJslDLoMg32feyWC5cgKHqG3AOO0OrBMnLMX6nCN5abWuukZu1+DpHkuHU9nqyFsSg k8YIcWrVLTrzLkmemCeXHhCgbyRuo6sucLKwmUPAiqns48oehwLUDCvrynq8gYYfWvQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794549876; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=Rj1etvk7gt7kIxdimWxsK6vzr3EEp81Rue5iwbWrWUU=; b=LbXgaFisSVevz4mzBQoU/DUf25vf7o0fA0w03CVi9XuDFd90wymoBukETBBgL67nLJRP FyIf0g3Vo9nOsN4fuPWtxtg3CQYgOmX8c5+eDA0ntoUDnp4H/e4h/Ssnm2eKSfe9YvUJe nanj4QXMZoZmdRtLqLsU6G/PuVou1Z8fpXhuQdNHt6Yi/n4Ys2GVb85bLG/U4lP8uIqyf F6TdjJP8fXb1Q7M6taxlSW1Rw564eBQeTxPPcz52D8WCGRBbskzs5HFblJkdac1WkXc9F 68Bvr4dfc21QC2+0+3mdhd64N+ZU8xbe4PqwWy3Vb/0VsLv9AzJYJr2BIbVcZzXcsww== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=o20+ygNM; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0321606A31C for ; Fri, 13 Nov 2026 06:04:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=o20+ygNM Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B3D21F000C4; Fri, 13 Nov 2026 06:04:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794549876; bh=Rj1etvk7gt7kIxdimWxsK6vzr3EEp81Rue5iwbWrWUU=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=o20+ygNMRJR1uV/N4bv9GMvwqHn9HuVIzgDu1V3hy1IVxoaRFSOHno76eRTPbd9E5 63WkwHZXcUXqktLJ0zfndP4YdKncFXpZbr0hAxmKNlmXSkh7BDLycLhBlisLCFLgRV wwuUY8mMkUVHQ17YbKhQON5werv8LBNXJh/XXkieC8GSA3sW1nACbyi9DKhEhSRH6a HQFNOq8YdjciyTV3ungrEQ/3bgFsLBPEFz1bvgeqtK+ytmuUatD7zTmQ6ovGgFqbW2 RR9G7g/DhRapdF5Ubq7vf8tgd3OD215NNzi2CIJ+uDt4a7y649x1FrvaCs/JxFCeQ1 q4g5+1EGExfhw== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v25 09/15] media: qcom: camss: csid: Add support for CSID 1080 Reply-To: sashiko-reviews@lists.linux.dev To: "Hangxiang Ma" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, media-ci@linuxtv.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261112-kaanapali-camss-v25-9-1d709f57f370@oss.qualcomm.com> References: <20261112-kaanapali-camss-v25-0-1d709f57f370@oss.qualcomm.com> <20261112-kaanapali-camss-v25-9-1d709f57f370@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Fri, 13 Nov 2026 06:04:35 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 6 potential issues to consider: - [High] media: qcom: camss: unconditional AUP triggers in csid_configure_stream() - [Medium] media: qcom: camss: out-of-bounds csid->fmt access in __csid_configure_rdi_stream() - [Medium] media: qcom: camss: race on addr_update and reg_update in csid_isr() - [Medium] media: qcom: camss: stale update state and IRQ mask in csid_reset() - [Low] media: qcom: camss: unused variable lane_cnt in __csid_configure_rdi_stream() - [Low] media: qcom: camss: malformed kernel-doc Return in csid_isr() and csid_reset() -- commit 259ca3091478f035f17a018767773d2d4fcaa553 Author: Hangxiang Ma media: qcom: camss: csid: Add support for CSID 1080 This commit adds hardware resource definitions and CSID 1080 operations for the Qualcomm Kaanapali SoC, including separate RUP and AUP register update handling and BUF_DONE interrupt processing. > diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.c b/driver= s/media/platform/qcom/camss/camss-csid-1080.c > new file mode 100644 > index 0000000000000..3d90d31201fa5 > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-csid-1080.c > @@ -0,0 +1,402 @@ [ ... ] > +#define MSM_CSID_MAX_SRC_STREAMS_1080 (csid_is_lite(csid) ? 4 : 5) [ ... ] > +static void __csid_aup_rup_trigger(struct csid_device *csid) > +{ > + /* trigger SET in combined register */ > + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); > +} > + > +static void __csid_addr_update(struct csid_device *csid, int port_id) > +{ > + csid->addr_update |=3D CSID_RUP_AUP_RDI(port_id); > + writel(csid->addr_update, csid->base + CSID_AUP_CMD); > + > + __csid_aup_rup_trigger(csid); > +} > + > +static void __csid_addr_update_clear(struct csid_device *csid, int port_= id) > +{ > + csid->addr_update &=3D ~CSID_RUP_AUP_RDI(port_id); > +} > + > +static void __csid_reg_update(struct csid_device *csid, int port_id) > +{ > + csid->reg_update |=3D CSID_RUP_AUP_RDI(port_id); > + writel(csid->reg_update, csid->base + CSID_RUP_CMD); > + > + __csid_aup_rup_trigger(csid); > +} > + > +static void __csid_reg_update_clear(struct csid_device *csid, int port_i= d) > +{ > + csid->reg_update &=3D ~CSID_RUP_AUP_RDI(port_id); > +} [ ... ] > +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 ena= ble, u8 port, u8 vc) > +{ > + u8 lane_cnt =3D csid->phy.lane_cnt; > + u32 val; > + > + /* Source pads matching RDI channels on hardware. > + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. > + */ > + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIR= ST_SRC + port]; > + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res-= >formats->formats, > + csid->res->formats->nformats, > + input_format->code); [Severity: Medium] Can this read past the end of csid->fmt[] on non-lite CSID 1080 instances? MSM_CSID_MAX_SRC_STREAMS_1080 is 5 when csid_is_lite(csid) is false, so csid_configure_stream() passes port =3D 4 into __csid_configure_rdi_stream(= ). However, MSM_CSID_PADS_NUM in drivers/media/platform/qcom/camss/camss-csid.h is 5 (1 sink pad and 4 source pads), sizing both csid->pads[] and csid->fmt[] to 5 elements: drivers/media/platform/qcom/camss/camss-csid.h: #define MSM_CSID_PAD_SINK 0 #define MSM_CSID_PAD_FIRST_SRC 1 #define MSM_CSID_PADS_NUM 5 When port is 4, MSM_CSID_PAD_FIRST_SRC + port is 5, which indexes one element past csid->fmt[5] (and the 5th RDI stream has no media pad registered by msm_csid_register_entity()). > + > + if (!lane_cnt) > + lane_cnt =3D 4; [Severity: Low] lane_cnt is initialized and updated here, but never used in __csid_configure_rdi_stream(), which triggers a -Wunused-but-set-variable warning under W=3D1 builds. [ ... ] > +static void csid_configure_stream(struct csid_device *csid, u8 enable) > +{ > + u8 i, k; > + > + __csid_configure_rx(csid, &csid->phy); > + > + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + __csid_configure_rdi_stream(csid, enable, i, 0); > + __csid_configure_rx_vc(csid, 0); > + > + for (k =3D 0; k < CAMSS_INIT_BUF_COUNT; k++) > + __csid_addr_update(csid, i); > + > + __csid_reg_update(csid, i); > + > + __csid_ctrl_rdi(csid, enable, i); > + } > + } > +} [Severity: High] Does unconditionally calling __csid_addr_update() CAMSS_INIT_BUF_COUNT times here latch uninitialized or duplicate buffer addresses into the hardware FIFO? During VIDIOC_STREAMON, video_start_streaming() runs vfe_enable_output_v2() before starting the CSID subdevice: drivers/media/platform/qcom/camss/camss-vfe.c:vfe_enable_output_v2() { ... for (i =3D 0; i < CAMSS_INIT_BUF_COUNT; i++) { output->buf[i] =3D vfe_buf_get_pending(output); if (!output->buf[i]) break; output->gen2.active_num++; ops->vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); if (!ops->addr_update) ops->reg_update(vfe, line->id); } ... } Because the vb2_queue does not set min_queued_buffers, 0, 1, or 2 buffers may be queued when streaming starts. If 0 or 1 buffers are pending, vfe_enable_output_v2() programs fewer than 2 addresses, yet csid_configure_stream() still triggers 2 AUPs (and also does so when enable =3D=3D 0). If 2 buffers are pending, the second ops->vfe_wm_update() overwrites VFE_BUS_WM_IMAGE_ADDR with buf[1]->addr[0] before any AUP has latched buf[0]->addr[0], and csid_configure_stream() then latches buf[1]->addr[0] twice. [ ... ] > +/** > + * csid_isr - CSID module interrupt service routine > + * @irq: Interrupt line > + * @dev: CSID device > + * > + * Return IRQ_HANDLED on success > + */ > +static irqreturn_t csid_isr(int irq, void *dev) > +{ > + struct csid_device *csid =3D dev; > + u32 val, buf_done_val; > + u8 reset_done; > + int i; > + > + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); > + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); > + > + reset_done =3D val & INFO_RST_DONE; > + > + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); > + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); > + > + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); > + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); > + > + if (val & INFO_RUP_DONE) { > + __csid_addr_update_clear(csid, i); > + __csid_reg_update_clear(csid, i); > + } > + > + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) > + camss_buf_done(csid->camss, csid->id, i); > + } > + } [Severity: Medium] As reported by bod@kernel.org on v24 [1], can concurrent updates to csid->addr_update and csid->reg_update race between process context and csid_isr()? Process context (VIDIOC_QBUF -> vfe_queue_buffer_v2() under vfe->output_lock, or csid_configure_stream() without locking) and csid_isr() perform unsynchronized read-modify-write updates on csid->addr_update and csid->reg_update and write the multi-port bitmask to CSID_AUP_CMD and CSID_RUP_CMD: CPU0 (process) CPU1 () vfe_queue_buffer_v2() spin_lock_irqsave(&vfe->output_lock) __csid_addr_update(csid, 0) reg =3D csid->addr_update csid_isr() __csid_addr_update_clear(csid, 1) csid->addr_update &=3D ~BIT(9) csid->addr_update =3D reg | BIT(8) writel(csid->addr_update, ...) <-- re-sets stale BIT(9) An interrupt on another CPU can also lose the newly set bit if the store in __csid_addr_update_clear() lands last. In addition, inside the csid_isr() loop, camss_buf_done() for port i calls vfe_buf_done() -> __csid_addr_update() before higher-numbered ports j > i have had INFO_RUP_DONE checked and cleared, writing their still-set bits back to CSID_AUP_CMD and CSID_RUP_CMD. [ ... ] > +/** > + * csid_reset - Trigger reset on CSID module and wait to complete > + * @csid: CSID device > + * > + * Return 0 on success or a negative error code otherwise > + */ [Severity: Low] The kernel-doc comments above csid_isr() and csid_reset() use "Return" instead of "Return:", which causes scripts/kernel-doc to warn that no return value description was found. > +static int csid_reset(struct csid_device *csid) > +{ > + unsigned long time; > + u32 val; > + int i; > + > + reinit_completion(&csid->reset_complete); > + > + val =3D INFO_RST_DONE | BUF_DONE_IRQ_STATUS; > + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); > + writel(val, csid->base + CSID_TOP_IRQ_MASK); > + > + val =3D 0; > + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + /* > + * Only need to clear buf done IRQ status here, > + * RUP done IRQ status will be cleared once isr > + * strobe generated by CSID_RST_CMD > + */ > + val |=3D BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); > + } > + } > + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); > + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); [Severity: Medium] Can csid_reset() leave stale bits in csid->addr_update and csid->reg_update, or leave CSID_BUF_DONE_IRQ_MASK masked for RDI ports linked after power-on? When csid_isr() handles a buffer completion, camss_buf_done() -> vfe_buf_done() sets csid->addr_update and csid->reg_update for the next buffer, and CSID_CSI2_RDIN_IRQ_MASK is never unmasked to deliver a standalone INFO_RUP_DONE interrupt. When streaming stops and a port is unlinked, neither csid_configure_stream() nor csid_reset() clears csid->addr_update or csid->reg_update, so starting a different RDI port later re-issues AUP and RUP commands for the stopped port. Furthermore, CSID_BUF_DONE_IRQ_MASK is only programmed here in csid_reset() from the bits set in csid->phy.en_vc at power-on time, and is never updated in csid_configure_stream(). If a second RDI link is enabled via MEDIA_IOC_SETUP_LINK while the CSID entity is already powered, CSID_BUF_DONE_IRQ_MASK remains masked for that port and buffer completions stall. [1] https://lore.kernel.org/r/179406039659.650304.183461297349639175.b4-rep= ly@b4 --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261112-kaanapali-= camss-v25-0-1d709f57f370@oss.qualcomm.com?part=3D9 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6D45606A32D for ; Fri, 13 Nov 2026 06:04:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=DRU3Eh4H; dkim=fail reason="signature verification failed" (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=o20+ygNM DKIM-Signature: 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HQFNOq8YdjciyTV3ungrEQ/3bgFsLBPEFz1bvgeqtK+ytmuUatD7zTmQ6ovGgFqbW2 RR9G7g/DhRapdF5Ubq7vf8tgd3OD215NNzi2CIJ+uDt4a7y649x1FrvaCs/JxFCeQ1 q4g5+1EGExfhw== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v25 09/15] media: qcom: camss: csid: Add support for CSID 1080 To: "Hangxiang Ma" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, media-ci@linuxtv.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261112-kaanapali-camss-v25-9-1d709f57f370@oss.qualcomm.com> References: <20261112-kaanapali-camss-v25-0-1d709f57f370@oss.qualcomm.com> <20261112-kaanapali-camss-v25-9-1d709f57f370@oss.qualcomm.com> Date: Fri, 13 Nov 2026 06:04:35 +0000 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: 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YXRlIGFuZCBJUlEgbWFzayBpbgogIGNzaWRfcmVzZXQoKQotIFtMb3ddIG1lZGlhOiBxY29tOiBj YW1zczogdW51c2VkIHZhcmlhYmxlIGxhbmVfY250IGluCiAgX19jc2lkX2NvbmZpZ3VyZV9yZGlf c3RyZWFtKCkKLSBbTG93XSBtZWRpYTogcWNvbTogY2Ftc3M6IG1hbGZvcm1lZCBrZXJuZWwtZG9j IFJldHVybiBpbiBjc2lkX2lzcigpCiAgYW5kIGNzaWRfcmVzZXQoKQotLQoKY29tbWl0IDI1OWNh MzA5MTQ3OGYwMzVmMTdhMDE4NzY3NzczZDJkNGZjYWE1NTMKQXV0aG9yOiBIYW5neGlhbmcgTWEg PGhhbmd4aWFuZy5tYUBvc3MucXVhbGNvbW0uY29tPgoKbWVkaWE6IHFjb206IGNhbXNzOiBjc2lk OiBBZGQgc3VwcG9ydCBmb3IgQ1NJRCAxMDgwCgpUaGlzIGNvbW1pdCBhZGRzIGhhcmR3YXJlIHJl c291cmNlIGRlZmluaXRpb25zIGFuZCBDU0lEIDEwODAgb3BlcmF0aW9ucyBmb3IKdGhlIFF1YWxj b21tIEthYW5hcGFsaSBTb0MsIGluY2x1ZGluZyBzZXBhcmF0ZSBSVVAgYW5kIEFVUCByZWdpc3Rl ciB1cGRhdGUKaGFuZGxpbmcgYW5kIEJVRl9ET05FIGludGVycnVwdCBwcm9jZXNzaW5nLgoKPiBk aWZmIC0tZ2l0IGEvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNzLWNzaWQt MTA4MC5jIGIvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNzLWNzaWQtMTA4 MC5jCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAwLi4zZDkwZDMx MjAxZmE1Cj4gLS0tIC9kZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0vcWNv bS9jYW1zcy9jYW1zcy1jc2lkLTEwODAuYwo+IEBAIC0wLDAgKzEsNDAyIEBACgpbIC4uLiBdCgo+ ICsjZGVmaW5lIE1TTV9DU0lEX01BWF9TUkNfU1RSRUFNU18xMDgwCQkoY3NpZF9pc19saXRlKGNz aWQpID8gNCA6IDUpCgpbIC4uLiBdCgo+ICtzdGF0aWMgdm9pZCBfX2NzaWRfYXVwX3J1cF90cmln Z2VyKHN0cnVjdCBjc2lkX2RldmljZSAqY3NpZCkKPiArewo+ICsJLyogdHJpZ2dlciBTRVQgaW4g Y29tYmluZWQgcmVnaXN0ZXIgKi8KPiArCXdyaXRlbChSVVBfU0VULCBjc2lkLT5iYXNlICsgQ1NJ RF9SVVBfQVVQX0NNRCk7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIF9fY3NpZF9hZGRyX3VwZGF0 ZShzdHJ1Y3QgY3NpZF9kZXZpY2UgKmNzaWQsIGludCBwb3J0X2lkKQo+ICt7Cj4gKwljc2lkLT5h ZGRyX3VwZGF0ZSB8PSBDU0lEX1JVUF9BVVBfUkRJKHBvcnRfaWQpOwo+ICsJd3JpdGVsKGNzaWQt PmFkZHJfdXBkYXRlLCBjc2lkLT5iYXNlICsgQ1NJRF9BVVBfQ01EKTsKPiArCj4gKwlfX2NzaWRf YXVwX3J1cF90cmlnZ2VyKGNzaWQpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBfX2NzaWRfYWRk cl91cGRhdGVfY2xlYXIoc3RydWN0IGNzaWRfZGV2aWNlICpjc2lkLCBpbnQgcG9ydF9pZCkKPiAr ewo+ICsJY3NpZC0+YWRkcl91cGRhdGUgJj0gfkNTSURfUlVQX0FVUF9SREkocG9ydF9pZCk7Cj4g K30KPiArCj4gK3N0YXRpYyB2b2lkIF9fY3NpZF9yZWdfdXBkYXRlKHN0cnVjdCBjc2lkX2Rldmlj ZSAqY3NpZCwgaW50IHBvcnRfaWQpCj4gK3sKPiArCWNzaWQtPnJlZ191cGRhdGUgfD0gQ1NJRF9S VVBfQVVQX1JESShwb3J0X2lkKTsKPiArCXdyaXRlbChjc2lkLT5yZWdfdXBkYXRlLCBjc2lkLT5i YXNlICsgQ1NJRF9SVVBfQ01EKTsKPiArCj4gKwlfX2NzaWRfYXVwX3J1cF90cmlnZ2VyKGNzaWQp Owo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBfX2NzaWRfcmVnX3VwZGF0ZV9jbGVhcihzdHJ1Y3Qg Y3NpZF9kZXZpY2UgKmNzaWQsIGludCBwb3J0X2lkKQo+ICt7Cj4gKwljc2lkLT5yZWdfdXBkYXRl ICY9IH5DU0lEX1JVUF9BVVBfUkRJKHBvcnRfaWQpOwo+ICt9CgpbIC4uLiBdCgo+ICtzdGF0aWMg dm9pZCBfX2NzaWRfY29uZmlndXJlX3JkaV9zdHJlYW0oc3RydWN0IGNzaWRfZGV2aWNlICpjc2lk LCB1OCBlbmFibGUsIHU4IHBvcnQsIHU4IHZjKQo+ICt7Cj4gKwl1OCBsYW5lX2NudCA9IGNzaWQt PnBoeS5sYW5lX2NudDsKPiArCXUzMiB2YWw7Cj4gKwo+ICsJLyogU291cmNlIHBhZHMgbWF0Y2hp bmcgUkRJIGNoYW5uZWxzIG9uIGhhcmR3YXJlLgo+ICsJICogRS5nLiBQYWQgMSAtPiBSREkwLCBQ YWQgMiAtPiBSREkxLCBldGMuCj4gKwkgKi8KPiArCXN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQg KmlucHV0X2Zvcm1hdCA9ICZjc2lkLT5mbXRbTVNNX0NTSURfUEFEX0ZJUlNUX1NSQyArIHBvcnRd Owo+ICsJY29uc3Qgc3RydWN0IGNzaWRfZm9ybWF0X2luZm8gKmZvcm1hdCA9IGNzaWRfZ2V0X2Zt dF9lbnRyeShjc2lkLT5yZXMtPmZvcm1hdHMtPmZvcm1hdHMsCj4gKwkJCQkJCQkJICAgY3NpZC0+ cmVzLT5mb3JtYXRzLT5uZm9ybWF0cywKPiArCQkJCQkJCQkgICBpbnB1dF9mb3JtYXQtPmNvZGUp OwoKW1NldmVyaXR5OiBNZWRpdW1dCkNhbiB0aGlzIHJlYWQgcGFzdCB0aGUgZW5kIG9mIGNzaWQt PmZtdFtdIG9uIG5vbi1saXRlIENTSUQgMTA4MCBpbnN0YW5jZXM/CgpNU01fQ1NJRF9NQVhfU1JD X1NUUkVBTVNfMTA4MCBpcyA1IHdoZW4gY3NpZF9pc19saXRlKGNzaWQpIGlzIGZhbHNlLCBzbwpj c2lkX2NvbmZpZ3VyZV9zdHJlYW0oKSBwYXNzZXMgcG9ydCA9IDQgaW50byBfX2NzaWRfY29uZmln dXJlX3JkaV9zdHJlYW0oKS4KSG93ZXZlciwgTVNNX0NTSURfUEFEU19OVU0gaW4gZHJpdmVycy9t ZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNzLWNzaWQuaAppcyA1ICgxIHNpbmsgcGFkIGFu ZCA0IHNvdXJjZSBwYWRzKSwgc2l6aW5nIGJvdGggY3NpZC0+cGFkc1tdIGFuZApjc2lkLT5mbXRb XSB0byA1IGVsZW1lbnRzOgoKZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNz LWNzaWQuaDoKICAgICNkZWZpbmUgTVNNX0NTSURfUEFEX1NJTksgMAogICAgI2RlZmluZSBNU01f Q1NJRF9QQURfRklSU1RfU1JDIDEKICAgICNkZWZpbmUgTVNNX0NTSURfUEFEU19OVU0gNQoKV2hl biBwb3J0IGlzIDQsIE1TTV9DU0lEX1BBRF9GSVJTVF9TUkMgKyBwb3J0IGlzIDUsIHdoaWNoIGlu ZGV4ZXMgb25lCmVsZW1lbnQgcGFzdCBjc2lkLT5mbXRbNV0gKGFuZCB0aGUgNXRoIFJESSBzdHJl YW0gaGFzIG5vIG1lZGlhIHBhZApyZWdpc3RlcmVkIGJ5IG1zbV9jc2lkX3JlZ2lzdGVyX2VudGl0 eSgpKS4KCj4gKwo+ICsJaWYgKCFsYW5lX2NudCkKPiArCQlsYW5lX2NudCA9IDQ7CgpbU2V2ZXJp dHk6IExvd10KbGFuZV9jbnQgaXMgaW5pdGlhbGl6ZWQgYW5kIHVwZGF0ZWQgaGVyZSwgYnV0IG5l dmVyIHVzZWQgaW4KX19jc2lkX2NvbmZpZ3VyZV9yZGlfc3RyZWFtKCksIHdoaWNoIHRyaWdnZXJz IGEgLVd1bnVzZWQtYnV0LXNldC12YXJpYWJsZQp3YXJuaW5nIHVuZGVyIFc9MSBidWlsZHMuCgpb IC4uLiBdCgo+ICtzdGF0aWMgdm9pZCBjc2lkX2NvbmZpZ3VyZV9zdHJlYW0oc3RydWN0IGNzaWRf ZGV2aWNlICpjc2lkLCB1OCBlbmFibGUpCj4gK3sKPiArCXU4IGksIGs7Cj4gKwo+ICsJX19jc2lk X2NvbmZpZ3VyZV9yeChjc2lkLCAmY3NpZC0+cGh5KTsKPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwg TVNNX0NTSURfTUFYX1NSQ19TVFJFQU1TXzEwODA7IGkrKykgewo+ICsJCWlmIChjc2lkLT5waHku ZW5fdmMgJiBCSVQoaSkpIHsKPiArCQkJX19jc2lkX2NvbmZpZ3VyZV9yZGlfc3RyZWFtKGNzaWQs IGVuYWJsZSwgaSwgMCk7Cj4gKwkJCV9fY3NpZF9jb25maWd1cmVfcnhfdmMoY3NpZCwgMCk7Cj4g Kwo+ICsJCQlmb3IgKGsgPSAwOyBrIDwgQ0FNU1NfSU5JVF9CVUZfQ09VTlQ7IGsrKykKPiArCQkJ CV9fY3NpZF9hZGRyX3VwZGF0ZShjc2lkLCBpKTsKPiArCj4gKwkJCV9fY3NpZF9yZWdfdXBkYXRl KGNzaWQsIGkpOwo+ICsKPiArCQkJX19jc2lkX2N0cmxfcmRpKGNzaWQsIGVuYWJsZSwgaSk7Cj4g KwkJfQo+ICsJfQo+ICt9CgpbU2V2ZXJpdHk6IEhpZ2hdCkRvZXMgdW5jb25kaXRpb25hbGx5IGNh bGxpbmcgX19jc2lkX2FkZHJfdXBkYXRlKCkgQ0FNU1NfSU5JVF9CVUZfQ09VTlQKdGltZXMgaGVy ZSBsYXRjaCB1bmluaXRpYWxpemVkIG9yIGR1cGxpY2F0ZSBidWZmZXIgYWRkcmVzc2VzIGludG8g dGhlCmhhcmR3YXJlIEZJRk8/CgpEdXJpbmcgVklESU9DX1NUUkVBTU9OLCB2aWRlb19zdGFydF9z dHJlYW1pbmcoKSBydW5zIHZmZV9lbmFibGVfb3V0cHV0X3YyKCkKYmVmb3JlIHN0YXJ0aW5nIHRo ZSBDU0lEIHN1YmRldmljZToKCmRyaXZlcnMvbWVkaWEvcGxhdGZvcm0vcWNvbS9jYW1zcy9jYW1z cy12ZmUuYzp2ZmVfZW5hYmxlX291dHB1dF92MigpIHsKICAgIC4uLgoJZm9yIChpID0gMDsgaSA8 IENBTVNTX0lOSVRfQlVGX0NPVU5UOyBpKyspIHsKCQlvdXRwdXQtPmJ1ZltpXSA9IHZmZV9idWZf Z2V0X3BlbmRpbmcob3V0cHV0KTsKCQlpZiAoIW91dHB1dC0+YnVmW2ldKQoJCQlicmVhazsKCQlv dXRwdXQtPmdlbjIuYWN0aXZlX251bSsrOwoJCW9wcy0+dmZlX3dtX3VwZGF0ZSh2ZmUsIG91dHB1 dC0+d21faWR4WzBdLAoJCQkJICAgb3V0cHV0LT5idWZbaV0tPmFkZHJbMF0sIGxpbmUpOwoJCWlm ICghb3BzLT5hZGRyX3VwZGF0ZSkKCQkJb3BzLT5yZWdfdXBkYXRlKHZmZSwgbGluZS0+aWQpOwoJ fQogICAgLi4uCn0KCkJlY2F1c2UgdGhlIHZiMl9xdWV1ZSBkb2VzIG5vdCBzZXQgbWluX3F1ZXVl ZF9idWZmZXJzLCAwLCAxLCBvciAyIGJ1ZmZlcnMKbWF5IGJlIHF1ZXVlZCB3aGVuIHN0cmVhbWlu ZyBzdGFydHMuIElmIDAgb3IgMSBidWZmZXJzIGFyZSBwZW5kaW5nLAp2ZmVfZW5hYmxlX291dHB1 dF92MigpIHByb2dyYW1zIGZld2VyIHRoYW4gMiBhZGRyZXNzZXMsIHlldApjc2lkX2NvbmZpZ3Vy ZV9zdHJlYW0oKSBzdGlsbCB0cmlnZ2VycyAyIEFVUHMgKGFuZCBhbHNvIGRvZXMgc28gd2hlbgpl bmFibGUgPT0gMCkuIElmIDIgYnVmZmVycyBhcmUgcGVuZGluZywgdGhlIHNlY29uZCBvcHMtPnZm ZV93bV91cGRhdGUoKQpvdmVyd3JpdGVzIFZGRV9CVVNfV01fSU1BR0VfQUREUiB3aXRoIGJ1Zlsx XS0+YWRkclswXSBiZWZvcmUgYW55IEFVUCBoYXMKbGF0Y2hlZCBidWZbMF0tPmFkZHJbMF0sIGFu ZCBjc2lkX2NvbmZpZ3VyZV9zdHJlYW0oKSB0aGVuIGxhdGNoZXMKYnVmWzFdLT5hZGRyWzBdIHR3 aWNlLgoKWyAuLi4gXQoKPiArLyoqCj4gKyAqIGNzaWRfaXNyIC0gQ1NJRCBtb2R1bGUgaW50ZXJy dXB0IHNlcnZpY2Ugcm91dGluZQo+ICsgKiBAaXJxOiBJbnRlcnJ1cHQgbGluZQo+ICsgKiBAZGV2 OiBDU0lEIGRldmljZQo+ICsgKgo+ICsgKiBSZXR1cm4gSVJRX0hBTkRMRUQgb24gc3VjY2Vzcwo+ ICsgKi8KPiArc3RhdGljIGlycXJldHVybl90IGNzaWRfaXNyKGludCBpcnEsIHZvaWQgKmRldikK PiArewo+ICsJc3RydWN0IGNzaWRfZGV2aWNlICpjc2lkID0gZGV2Owo+ICsJdTMyIHZhbCwgYnVm X2RvbmVfdmFsOwo+ICsJdTggcmVzZXRfZG9uZTsKPiArCWludCBpOwo+ICsKPiArCXZhbCA9IHJl YWRsKGNzaWQtPmJhc2UgKyBDU0lEX1RPUF9JUlFfU1RBVFVTKTsKPiArCXdyaXRlbCh2YWwsIGNz aWQtPmJhc2UgKyBDU0lEX1RPUF9JUlFfQ0xFQVIpOwo+ICsKPiArCXJlc2V0X2RvbmUgPSB2YWwg JiBJTkZPX1JTVF9ET05FOwo+ICsKPiArCWJ1Zl9kb25lX3ZhbCA9IHJlYWRsKGNzaWQtPmJhc2Ug KyBDU0lEX0JVRl9ET05FX0lSUV9TVEFUVVMpOwo+ICsJd3JpdGVsKGJ1Zl9kb25lX3ZhbCwgY3Np ZC0+YmFzZSArIENTSURfQlVGX0RPTkVfSVJRX0NMRUFSKTsKPiArCj4gKwlmb3IgKGkgPSAwOyBp IDwgTVNNX0NTSURfTUFYX1NSQ19TVFJFQU1TXzEwODA7IGkrKykgewo+ICsJCWlmIChjc2lkLT5w aHkuZW5fdmMgJiBCSVQoaSkpIHsKPiArCQkJdmFsID0gcmVhZGwoY3NpZC0+YmFzZSArIENTSURf Q1NJMl9SRElOX0lSUV9TVEFUVVMoaSkpOwo+ICsJCQl3cml0ZWwodmFsLCBjc2lkLT5iYXNlICsg Q1NJRF9DU0kyX1JESU5fSVJRX0NMRUFSKGkpKTsKPiArCj4gKwkJCWlmICh2YWwgJiBJTkZPX1JV UF9ET05FKSB7Cj4gKwkJCQlfX2NzaWRfYWRkcl91cGRhdGVfY2xlYXIoY3NpZCwgaSk7Cj4gKwkJ CQlfX2NzaWRfcmVnX3VwZGF0ZV9jbGVhcihjc2lkLCBpKTsKPiArCQkJfQo+ICsKPiArCQkJaWYg KGJ1Zl9kb25lX3ZhbCAmIEJJVChCVUZfRE9ORV9JUlFfU1RBVFVTX1JESV9PRkZTRVQgKyBpKSkK PiArCQkJCWNhbXNzX2J1Zl9kb25lKGNzaWQtPmNhbXNzLCBjc2lkLT5pZCwgaSk7Cj4gKwkJfQo+ ICsJfQoKW1NldmVyaXR5OiBNZWRpdW1dCkFzIHJlcG9ydGVkIGJ5IGJvZEBrZXJuZWwub3JnIG9u IHYyNCBbMV0sIGNhbiBjb25jdXJyZW50IHVwZGF0ZXMgdG8KY3NpZC0+YWRkcl91cGRhdGUgYW5k IGNzaWQtPnJlZ191cGRhdGUgcmFjZSBiZXR3ZWVuIHByb2Nlc3MgY29udGV4dCBhbmQKY3NpZF9p c3IoKT8KClByb2Nlc3MgY29udGV4dCAoVklESU9DX1FCVUYgLT4gdmZlX3F1ZXVlX2J1ZmZlcl92 MigpIHVuZGVyCnZmZS0+b3V0cHV0X2xvY2ssIG9yIGNzaWRfY29uZmlndXJlX3N0cmVhbSgpIHdp dGhvdXQgbG9ja2luZykgYW5kCmNzaWRfaXNyKCkgcGVyZm9ybSB1bnN5bmNocm9uaXplZCByZWFk LW1vZGlmeS13cml0ZSB1cGRhdGVzIG9uCmNzaWQtPmFkZHJfdXBkYXRlIGFuZCBjc2lkLT5yZWdf dXBkYXRlIGFuZCB3cml0ZSB0aGUgbXVsdGktcG9ydCBiaXRtYXNrIHRvCkNTSURfQVVQX0NNRCBh bmQgQ1NJRF9SVVBfQ01EOgoKQ1BVMCAocHJvY2VzcykgICAgICAgICAgICAgICAgICAgIENQVTEg KDxoYXJkaXJxPikKdmZlX3F1ZXVlX2J1ZmZlcl92MigpCiAgc3Bpbl9sb2NrX2lycXNhdmUoJnZm ZS0+b3V0cHV0X2xvY2spCiAgX19jc2lkX2FkZHJfdXBkYXRlKGNzaWQsIDApCiAgICByZWcgPSBj c2lkLT5hZGRyX3VwZGF0ZQogICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgY3NpZF9p c3IoKQogICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBfX2NzaWRfYWRkcl91cGRh dGVfY2xlYXIoY3NpZCwgMSkKICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBj c2lkLT5hZGRyX3VwZGF0ZSAmPSB+QklUKDkpCiAgICBjc2lkLT5hZGRyX3VwZGF0ZSA9IHJlZyB8 IEJJVCg4KQogICAgd3JpdGVsKGNzaWQtPmFkZHJfdXBkYXRlLCAuLi4pICA8LS0gcmUtc2V0cyBz dGFsZSBCSVQoOSkKCkFuIGludGVycnVwdCBvbiBhbm90aGVyIENQVSBjYW4gYWxzbyBsb3NlIHRo ZSBuZXdseSBzZXQgYml0IGlmIHRoZSBzdG9yZSBpbgpfX2NzaWRfYWRkcl91cGRhdGVfY2xlYXIo KSBsYW5kcyBsYXN0LiBJbiBhZGRpdGlvbiwgaW5zaWRlIHRoZSBjc2lkX2lzcigpCmxvb3AsIGNh bXNzX2J1Zl9kb25lKCkgZm9yIHBvcnQgaSBjYWxscyB2ZmVfYnVmX2RvbmUoKSAtPgpfX2NzaWRf YWRkcl91cGRhdGUoKSBiZWZvcmUgaGlnaGVyLW51bWJlcmVkIHBvcnRzIGogPiBpIGhhdmUgaGFk CklORk9fUlVQX0RPTkUgY2hlY2tlZCBhbmQgY2xlYXJlZCwgd3JpdGluZyB0aGVpciBzdGlsbC1z ZXQgYml0cyBiYWNrIHRvCkNTSURfQVVQX0NNRCBhbmQgQ1NJRF9SVVBfQ01ELgoKWyAuLi4gXQoK PiArLyoqCj4gKyAqIGNzaWRfcmVzZXQgLSBUcmlnZ2VyIHJlc2V0IG9uIENTSUQgbW9kdWxlIGFu ZCB3YWl0IHRvIGNvbXBsZXRlCj4gKyAqIEBjc2lkOiBDU0lEIGRldmljZQo+ICsgKgo+ICsgKiBS ZXR1cm4gMCBvbiBzdWNjZXNzIG9yIGEgbmVnYXRpdmUgZXJyb3IgY29kZSBvdGhlcndpc2UKPiAr ICovCgpbU2V2ZXJpdHk6IExvd10KVGhlIGtlcm5lbC1kb2MgY29tbWVudHMgYWJvdmUgY3NpZF9p c3IoKSBhbmQgY3NpZF9yZXNldCgpIHVzZSAiUmV0dXJuIgppbnN0ZWFkIG9mICJSZXR1cm46Iiwg d2hpY2ggY2F1c2VzIHNjcmlwdHMva2VybmVsLWRvYyB0byB3YXJuIHRoYXQgbm8KcmV0dXJuIHZh bHVlIGRlc2NyaXB0aW9uIHdhcyBmb3VuZC4KCj4gK3N0YXRpYyBpbnQgY3NpZF9yZXNldChzdHJ1 Y3QgY3NpZF9kZXZpY2UgKmNzaWQpCj4gK3sKPiArCXVuc2lnbmVkIGxvbmcgdGltZTsKPiArCXUz MiB2YWw7Cj4gKwlpbnQgaTsKPiArCj4gKwlyZWluaXRfY29tcGxldGlvbigmY3NpZC0+cmVzZXRf Y29tcGxldGUpOwo+ICsKPiArCXZhbCA9IElORk9fUlNUX0RPTkUgfCBCVUZfRE9ORV9JUlFfU1RB VFVTOwo+ICsJd3JpdGVsKHZhbCwgY3NpZC0+YmFzZSArIENTSURfVE9QX0lSUV9DTEVBUik7Cj4g Kwl3cml0ZWwodmFsLCBjc2lkLT5iYXNlICsgQ1NJRF9UT1BfSVJRX01BU0spOwo+ICsKPiArCXZh bCA9IDA7Cj4gKwlmb3IgKGkgPSAwOyBpIDwgTVNNX0NTSURfTUFYX1NSQ19TVFJFQU1TXzEwODA7 IGkrKykgewo+ICsJCWlmIChjc2lkLT5waHkuZW5fdmMgJiBCSVQoaSkpIHsKPiArCQkJLyoKPiAr CQkJICogT25seSBuZWVkIHRvIGNsZWFyIGJ1ZiBkb25lIElSUSBzdGF0dXMgaGVyZSwKPiArCQkJ ICogUlVQIGRvbmUgSVJRIHN0YXR1cyB3aWxsIGJlIGNsZWFyZWQgb25jZSBpc3IKPiArCQkJICog c3Ryb2JlIGdlbmVyYXRlZCBieSBDU0lEX1JTVF9DTUQKPiArCQkJICovCj4gKwkJCXZhbCB8PSBC SVQoQlVGX0RPTkVfSVJRX1NUQVRVU19SRElfT0ZGU0VUICsgaSk7Cj4gKwkJfQo+ICsJfQo+ICsJ d3JpdGVsKHZhbCwgY3NpZC0+YmFzZSArIENTSURfQlVGX0RPTkVfSVJRX0NMRUFSKTsKPiArCXdy aXRlbCh2YWwsIGNzaWQtPmJhc2UgKyBDU0lEX0JVRl9ET05FX0lSUV9NQVNLKTsKCltTZXZlcml0 eTogTWVkaXVtXQpDYW4gY3NpZF9yZXNldCgpIGxlYXZlIHN0YWxlIGJpdHMgaW4gY3NpZC0+YWRk cl91cGRhdGUgYW5kCmNzaWQtPnJlZ191cGRhdGUsIG9yIGxlYXZlIENTSURfQlVGX0RPTkVfSVJR X01BU0sgbWFza2VkIGZvciBSREkgcG9ydHMKbGlua2VkIGFmdGVyIHBvd2VyLW9uPwoKV2hlbiBj c2lkX2lzcigpIGhhbmRsZXMgYSBidWZmZXIgY29tcGxldGlvbiwgY2Ftc3NfYnVmX2RvbmUoKSAt Pgp2ZmVfYnVmX2RvbmUoKSBzZXRzIGNzaWQtPmFkZHJfdXBkYXRlIGFuZCBjc2lkLT5yZWdfdXBk YXRlIGZvciB0aGUgbmV4dApidWZmZXIsIGFuZCBDU0lEX0NTSTJfUkRJTl9JUlFfTUFTSyBpcyBu ZXZlciB1bm1hc2tlZCB0byBkZWxpdmVyIGEKc3RhbmRhbG9uZSBJTkZPX1JVUF9ET05FIGludGVy cnVwdC4gV2hlbiBzdHJlYW1pbmcgc3RvcHMgYW5kIGEgcG9ydCBpcwp1bmxpbmtlZCwgbmVpdGhl ciBjc2lkX2NvbmZpZ3VyZV9zdHJlYW0oKSBub3IgY3NpZF9yZXNldCgpIGNsZWFycwpjc2lkLT5h ZGRyX3VwZGF0ZSBvciBjc2lkLT5yZWdfdXBkYXRlLCBzbyBzdGFydGluZyBhIGRpZmZlcmVudCBS REkgcG9ydApsYXRlciByZS1pc3N1ZXMgQVVQIGFuZCBSVVAgY29tbWFuZHMgZm9yIHRoZSBzdG9w cGVkIHBvcnQuCgpGdXJ0aGVybW9yZSwgQ1NJRF9CVUZfRE9ORV9JUlFfTUFTSyBpcyBvbmx5IHBy b2dyYW1tZWQgaGVyZSBpbiBjc2lkX3Jlc2V0KCkKZnJvbSB0aGUgYml0cyBzZXQgaW4gY3NpZC0+ cGh5LmVuX3ZjIGF0IHBvd2VyLW9uIHRpbWUsIGFuZCBpcyBuZXZlciB1cGRhdGVkCmluIGNzaWRf Y29uZmlndXJlX3N0cmVhbSgpLiBJZiBhIHNlY29uZCBSREkgbGluayBpcyBlbmFibGVkIHZpYQpN RURJQV9JT0NfU0VUVVBfTElOSyB3aGlsZSB0aGUgQ1NJRCBlbnRpdHkgaXMgYWxyZWFkeSBwb3dl cmVkLApDU0lEX0JVRl9ET05FX0lSUV9NQVNLIHJlbWFpbnMgbWFza2VkIGZvciB0aGF0IHBvcnQg YW5kIGJ1ZmZlciBjb21wbGV0aW9ucwpzdGFsbC4KClsxXSBodHRwczovL2xvcmUua2VybmVsLm9y Zy9yLzE3OTQwNjAzOTY1OS42NTAzMDQuMTgzNDYxMjk3MzQ5NjM5MTc1LmI0LXJlcGx5QGI0Cgot LSAKU2FzaGlrbyBBSSByZXZpZXcgwrcgaHR0cHM6Ly9zYXNoaWtvLmRldi8jL3BhdGNoc2V0LzIw MjYxMTEyLWthYW5hcGFsaS1jYW1zcy12MjUtMC0xZDcwOWY1N2YzNzBAb3NzLnF1YWxjb21tLmNv bT9wYXJ0PTkKCi0tIApsaW51eC1waHkgbWFpbGluZyBsaXN0CmxpbnV4LXBoeUBsaXN0cy5pbmZy YWRlYWQub3JnCmh0dHBzOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp bnV4LXBoeQo=