All of lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Ce Sun" <cesun102@amd.com>, amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: skip uniras block ECC query in GPU reset path
Date: Fri, 13 Nov 2026 10:49:40 +0000	[thread overview]
Message-ID: <sashiko-outbox-212636@kernel.org> (raw)
In-Reply-To: <20261113095441.1604-1-cesun102@amd.com>

Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Medium] drm/amdgpu: incomplete reset check in
  amdgpu_persistent_edc_harvesting()
- [Low] drm/amdgpu: missing Fixes trailer for GPU reset ECC query
  regression
--

commit a877bda7a103d3656c06f840d5177c8e2b166cc8
Author: Ce Sun <cesun102@amd.com>

> drm/amdgpu: skip uniras block ECC query in GPU reset path
>
> amdgpu_uniras_query_block_ecc doesn't support being called during GPU reset.
>
> Signed-off-by: Ce Sun <cesun102@amd.com>
> Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>

[Severity: Low]
This fixes a GPU reset regression introduced when
amdgpu_ras_query_error_status() was wired to amdgpu_uniras_query_block_ecc().
Should this include:

  Fixes: fe2ccc7b7b23 ("drm/amdgpu: query block error count of ras module")

> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index 312566337ab14..6d8b2e24880f6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -3758,6 +3758,10 @@ static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
>  	if (!amdgpu_persistent_edc_harvesting_supported(adev))
>  		return 0;
>  
> +	if ((amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev)) &&
> +	     amdgpu_uniras_enabled(adev))
> +		return 0;
> +
>  	if (amdgpu_ras_query_error_status(adev, &info) != 0)
>  		drm_warn(adev_to_drm(adev), "RAS init query failure");
>  

[Severity: Medium]
Should this check skip the query during GPU reset regardless of
amdgpu_uniras_enabled(adev), matching amdgpu_ras_reset_error_count()?

During GPU reset (including amdgpu_xgmi_reset_on_init_work(), where the
RAS IP block has not yet run hw_init so amdgpu_uniras_enabled(adev)
returns false even on uniras devices), the reset thread holds
down_write(&adev->reset_domain->sem).  When amdgpu_uniras_enabled(adev) is
false, execution falls through to amdgpu_ras_query_error_status() ->
amdgpu_ras_query_error_status_with_event(), which fails
down_read_trylock(&adev->reset_domain->sem) with -EIO and logs a false
"RAS init query failure" warning for each RAS block.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261113095441.1604-1-cesun102@amd.com?part=1

  reply	other threads:[~2026-11-13 10:49 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-13  9:54 [PATCH] drm/amdgpu: skip uniras block ECC query in GPU reset path Ce Sun
2026-11-13 10:49 ` sashiko-bot [this message]
  -- strict thread matches above, loose matches on Subject: below --
2026-11-13  3:28 Ce Sun

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=sashiko-outbox-212636@kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=cesun102@amd.com \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.