Re: [PATCH v19 6/6] usb: dwc3: rockchip: add USBDP PHY reset quirk

[sashiko-bot@kernel.org]

> On recent Rockchip platforms (at least RK3588 & RK3576), DWC3 IP is used
> with a USBDP PHY providing USB3 and DP. This PHY needs to be reset when
> the mode changes, which may happen when plugging in different USB-C
> devices.
> 
> If the USBDP PHY resets with the DWC3 IP running, its internal state
> corrupts resulting in the USBDP PHY not being able to lock some PLL
> clocks, which effectively renders USB3 unusable.
> 
> To fix the issue this adds a Rockchip USBDP specific quirk, which will
> assert PHYSOFTRST before the actual PHY is disabled and will deassert it
> once the PHY returns.
> 
> The quirk is skipped while DWC3 is suspended, as its registers may be
> inaccessible and the device being suspended is a quirk in itself (the
> vendor BSP enables runtime PM with very short autosuspend as a
> workaround for this issue). Thus the code just ensures the PM state
> does not change while the PHY reset is going on.
> 
> Note, that the same platforms also use DWC3 with a different PHY
> (rockchip-naneng-combphy), so the PHY calls are protected by a
> driver name check.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Sashiko has reviewed this patch and found no issues.

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Sashiko AI review · https://sashiko.dev/#/patchset/20261114-b4-rockchip-dwc3-rockchip-glue-v19-0-b79fb5f4b42a@collabora.com?part=6