From: sashiko-bot@kernel.org
To: ElXreno <elxreno@gmail.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 1/7] drm/i915/panel: Fix the pixel clock overflow in the VRR vtotal
Date: Sat, 14 Nov 2026 01:54:42 +0000 [thread overview]
Message-ID: <sashiko-outbox-214017@kernel.org> (raw)
In-Reply-To: <20261114014335.2132756-2-elxreno@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] drm/i915/panel: commit Signed-off-by trailer uses handle
instead of real name
--
commit a81f42546a1b676a6932361ec102d9c524823aa2
Author: ElXreno <elxreno@gmail.com>
> drm/i915/panel: Fix the pixel clock overflow in the VRR vtotal
>
> intel_panel_compute_config_vrr() multiplies the pixel clock in kHz by
> 1000 in a signed int. A 3840x2400@240 timing has a 2342.4 MHz pixel
> clock, the product overflows, and the vertical total computed for a
> refresh rate other than that of the fixed mode comes out negative.
>
> Do the multiplication in 64 bits.
>
> This needs a fixed mode above 2147 MHz, so one that uses the joiner,
> inside the VRR range of the panel, and a request for another refresh
> rate that ends up on that fixed mode, as the allow_modeset=false path
> does for a mode that is VRR compatible with the current one.
>
> Fixes: a2da67028cd0 ("drm/i915: Allow arbitrary refresh rates with VRR eDP panels")
> Signed-off-by: ElXreno <elxreno@gmail.com>
[Severity: High]
Both the Author header and the Signed-off-by trailer use the single-word
handle ElXreno rather than a real full name. Documentation/process/submitting-patches.rst
requires contributors to sign off using a known real identity under the
Developer's Certificate of Origin rather than a pseudonym or handle.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114014335.2132756-1-elxreno@gmail.com?part=1
next prev parent reply other threads:[~2026-11-14 1:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-14 1:43 [PATCH 0/7] drm/i915: VRR with the pipe joiner ElXreno
2026-11-14 1:43 ` [PATCH 1/7] drm/i915/panel: Fix the pixel clock overflow in the VRR vtotal ElXreno
2026-11-14 1:54 ` sashiko-bot [this message]
2026-11-14 1:43 ` [PATCH 2/7] drm/i915/vrr: Fix the pixel clock overflow in the vmax computation ElXreno
2026-11-14 1:52 ` sashiko-bot
2026-11-14 1:43 ` [PATCH 3/7] drm/i915/vrr: Leave the transcoder to the joiner primary ElXreno
2026-11-14 1:56 ` sashiko-bot
2026-11-14 1:43 ` [PATCH 4/7] drm/i915: Split intel_update_crtc() into its stages ElXreno
2026-11-14 1:48 ` sashiko-bot
2026-11-14 1:43 ` [PATCH 5/7] drm/i915: Arm joined pipes within one vblank evasion for VRR ElXreno
2026-11-14 2:02 ` sashiko-bot
2026-11-14 1:43 ` [PATCH 6/7] drm/i915: Evade the vblank on the scanline of the joiner primary ElXreno
2026-11-14 1:53 ` sashiko-bot
2026-11-14 1:43 ` [PATCH 7/7] drm/i915/vrr: Allow VRR with the pipe joiner ElXreno
2026-11-14 2:24 ` sashiko-bot
2026-11-14 2:51 ` ElXreno
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