From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794657350; b=dEJjULmCbliLtlNFpTkGy3Jdp35YK1mcPr9QI9VTwDj+vCWQNvP9Avvt0O8tQkNS5UH4 c+tDC9H2yhajGGmfwAvCKMyeVKv2JHqN06tZzvYI5JidJNEKPpzckBPpWlEORPcsprdOc +ybhaRFnG4LZs4NxgotuecAXMfS9P20x/8NAQCbv2nSvKQlbGBC+GMwLa781DqhDMz10D +f4z8qrXx24Pg8sjBbYwm01PbpBfINJWHNiD+hOAL9JvJ7wMB6K6X28n/y4pBd7Fe7Uml WxzP65rqm/k4Uipp+2Y8tlwiwQXMxqZBNxAth90mh/mpqyskJfIiSJ6Vimh2P9NmT0w== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794657350; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=4/Q1bfzHfAdx4wt2Qbi+egQJKxl84zjDLUbFA3DRoSQ=; b=anKXFkmSwK2f8hd4QiRvUK6bhY6Bx+FcFMp6gtk7Xj+JGI6CDhT9LkkiwnW/TJu+64/s g2DFwQUMnOTXeIiykEZX6N+Y7Mpi1azKe/OqftozRXnsb5UMpGUXK53VlRM2F9csctbv0 HjEE9q0M5wiJo8F1hhjsXctJVRKLGc9mWDk8pXDCr5NWmdTtN90/K/2cRNinLvORifiM9 CzK5BankUhDJ5pzRyK2t13Cz+aQgVCZlW7ievOouX63MsobwFnoQN2fp4D9qr3YjYp8hJ dqEkX/0H1K/ray1iRqfLn2itScgeBe+j+0aoQabVusfJ8+/7XypPnSaT4GNppVtvFqg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b="Zahy/hNq"; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED07E606A327 for ; Sat, 14 Nov 2026 11:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=Zahy/hNq Received: by smtp.kernel.org (Postfix) with ESMTPSA id 154761F000C5; Sat, 14 Nov 2026 11:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794657349; bh=4/Q1bfzHfAdx4wt2Qbi+egQJKxl84zjDLUbFA3DRoSQ=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=Zahy/hNqmGQJOjs0QgTtqR8oGTtXJ8fNe5guB89mnjz002biupVowEMq5Olf9oKih EcAZTHdMEh4ao5TZTLh6LffeRBb7mqdcbjqrJgW8itLPuipSP8DWSd3NAcu/pGg1wz sM23i6E3/aEJoLbxbMdLa3+U473hiGJ36YmDxzpeaAMh4wZ/p8AJjAklz/HwQuPKK4 93LFjDFsj//Y5jevCVR5VujtQNbRkXuUVd3RD5cGvhxsXuwFX5TQ1i4qElFFiehuu8 XrhGazTCUy89P/71Q3rWi8gM5T/q8F8LUmoh9J+mv3ZJg+VxBD/PTgGJQpwRX7OVZW BWudybVwsq0LQ== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v7 10/23] media: qcom: camss: csid: Add support for CSID 980 Reply-To: sashiko-reviews@lists.linux.dev To: "Wenmeng Liu" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, media-ci@linuxtv.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261114-add-support-for-camss-on-sm8750-v7-10-8ff2a11835f6@oss.qualcomm.com> References: <20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com> <20261114-add-support-for-camss-on-sm8750-v7-10-8ff2a11835f6@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Sat, 14 Nov 2026 11:55:48 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 3 potential issues to consider: - [High] media: qcom: camss: wrong dt_id calculation in __csid_configure_rdi_stream() - [Medium] media: qcom: camss: misplaced lane_cnt fallback in camss-csid-980.c - [Medium] media: qcom: camss: race on csid->reg_update and addr_update in csid-980 -- commit ad1ff7fa26120bcd2005c8cf69d816599d94898f Author: Hangxiang Ma media: qcom: camss: csid: Add support for CSID 980 This commit adds the CSID 980 hardware operations driver and populates the SM8750 CSID subdevice resource definitions. > diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers= /media/platform/qcom/camss/camss-csid-980.c > new file mode 100644 > index 0000000000000..713db25cd8c65 > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-csid-980.c > @@ -0,0 +1,466 @@ [ ... ] > +static void __csid_configure_rx(struct csid_device *csid, > + struct csid_phy_config *phy) > +{ > + int val; > + > + val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; > + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; > + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) > + << CSI2_RX_CFG0_PHY_NUM_SEL; > + writel(val, csid->base + CSID_CSI2_RX_CFG0); > + > + val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; > + writel(val, csid->base + CSID_CSI2_RX_CFG1); > +} [ ... ] > +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 ena= ble, u8 port, u8 vc) > +{ > + u8 lane_cnt =3D csid->phy.lane_cnt; > + u32 val; > + > + /* Source pads matching RDI channels on hardware. > + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. > + */ > + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIR= ST_SRC + port]; > + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res-= >formats->formats, > + csid->res->formats->nformats, > + input_format->code); > + > + if (!lane_cnt) > + lane_cnt =3D 4; [Severity: Medium] Was the lane_cnt fallback meant to be in __csid_configure_rx() instead of __csid_configure_rdi_stream()? In __csid_configure_rdi_stream(), lane_cnt is never read after being set, which triggers a -Wunused-but-set-variable warning under W=3D1 (and precedes the variable declarations below). Meanwhile, __csid_configure_rx() uses phy->lane_cnt - 1 directly in signed int arithmetic, so if phy->lane_cnt is 0 (for instance, when csid_set_stream() disables a stream after csid_set_power() without an active sink link), val becomes -1 and corrupts all fields written to CSID_CSI2_RX_CFG0. > + > + /* > + * DT_ID is a two bit bitfield that is concatenated with > + * the four least significant bits of the five bit VC > + * bitfield to generate an internal CID value. > + * > + * CSID_RDI_CFG0(vc) > + * DT_ID : 28:27 > + * VC : 26:22 > + * DT : 21:16 > + * > + * CID : VC 3:0 << 2 | DT_ID 1:0 > + */ > + u8 dt_id =3D vc & 0x03; > + u32 rdi_cfg0_offset =3D CSID_RDI_CFG0(port); > + u32 rdi_cfg1_offset =3D CSID_RDI_CFG1(port); > + u32 rdi_ctrl_offset =3D CSID_RDI_CTRL(port); > + > + val =3D RDI_CFG0_TIMESTAMP_EN; > + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; > + val |=3D RDI_CFG0_RETIME_BS; > + > + /* note: for non-RDI path, this should be format->decode_format */ > + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; > + val |=3D vc << RDI_CFG0_VC; > + val |=3D format->data_type << RDI_CFG0_DT; > + val |=3D dt_id << RDI_CFG0_DT_ID; > + writel(val, csid->base + rdi_cfg0_offset); [ ... ] > +static void csid_configure_stream(struct csid_device *csid, u8 enable) > +{ > + u8 i, k; > + > + __csid_configure_rx(csid, &csid->phy); > + > + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + __csid_configure_rdi_stream(csid, enable, i, 0); [Severity: High] Should dt_id in __csid_configure_rdi_stream() be derived from port & 0x03 rather than vc & 0x03? csid_configure_stream() always passes vc =3D 0 while passing the RDI channel index i as port. Calculating dt_id from vc sets RDI_CFG0_DT_ID to 0 for every RDI channel, so RDI1, RDI2, and RDI3 all receive internal CID 0 and cannot stream properly, matching the issue fixed for CSID GEN3 in commit ad136e52634d ("media: qcom: camss: Fix RDI streaming for CSID GEN3") and for CSID GEN2 in commit 618765634cef ("media: qcom: camss: Fix RDI streaming for CSID GEN2"). [ ... ] > +static irqreturn_t csid_isr(int irq, void *dev) > +{ > + struct csid_device *csid =3D dev; > + u32 val, buf_done_val; > + u8 reset_done; > + int i; > + > + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); > + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); > + > + reset_done =3D val & INFO_RST_DONE; > + > + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); > + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); > + > + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); > + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); > + > + if (val & INFO_RUP_DONE) { > + __csid_addr_update_clear(csid, i); > + __csid_reg_update_clear(csid, i); > + } > + > + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) > + camss_buf_done(csid->camss, csid->id, i); > + } > + } [Severity: Medium] Can __csid_addr_update_clear() and __csid_reg_update_clear() in csid_isr() race with concurrent updates to csid->reg_update and csid->addr_update? In camss-vfe.c, vfe_queue_buffer_v2(), vfe_enable_output_v2(), and vfe_buf_done() hold vfe->output_lock while calling the CSID addr_update and reg_update callbacks, which perform non-atomic read-modify-write updates on csid->reg_update and csid->addr_update. However, csid_isr() clears bits in csid->addr_update and csid->reg_update before camss_buf_done() is called and without holding vfe->output_lock: CPU0 CPU1 () vfe_queue_buffer_v2() spin_lock_irqsave(&vfe->output_lock) __csid_addr_update(csid, i) csid->reg_update |=3D AUP_RDI(i) writel(csid->reg_update, CSID_LITE_RUP_AUP_CMD) csid_isr() if (val & INFO_RUP_DONE) __csid_addr_update_clear(csid, i) csid->reg_update &=3D ~AUP_RDI(i) __csid_reg_update(csid, i) csid->reg_update |=3D RUP_RDI(i) writel(csid->reg_update, ...) <-- overwrites CMD with AUP_RDI(i) cleared On CSID Lite, where RUP and AUP share csid->reg_update and the CSID_LITE_RUP_AUP_CMD register, this race can clear a newly queued AUP bit in hardware before it is consumed, and across multiple active RDI ports it can lose or retain stale update bits in csid->reg_update and csid->addr_update. --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261114-add-suppor= t-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=3D10 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C78AE606A32E for ; Sat, 14 Nov 2026 11:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=bHEX/dtU; dkim=fail reason="signature verification failed" (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=Zahy/hNq DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Date:References: In-Reply-To:Cc:To:Subject:From:Message-ID:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Unsubscribe-Post:List-Owner; bh=ni+GZbjD05Je7WORst2XifXFzK6/3q8uvCxdx9FaNm8=; b=bHEX/dtUMAFHvq+ur/0J5e7N8u r3AqPN3b2HGb7h5h8bqHlmO31Z7BYjVfOHA+Vswxn/uC2rOIosdUbM1yRCtztd9U986XdaP/DW/X5 c4M8yrNqOboylrRVXVJHfZDF1+UAvJzbBJJRc6cT/3gJK48oUxY6Ft10FOfzO3k9daP5iRSOR3WlO 9BGn0ETDF7MNXe8QH+I9KObVfLVtFxOqsm3vU4JIRuZcjO/GG5wWoyKSJ8bZSE+FsZI+cxkiRI4XC BW8JBPbaR2Ts7lUWdKM0ouxT8Bz7/e7JLz5qOEPRLeiRWWHgUfwfs0Rr0ZnVRTNGPAuH0f2eIPuJz V0ruFaGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xSCMK-0000000Fvu9-1X3u; Sat, 14 Nov 2026 11:55:52 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xSCMI-0000000FvtF-2keN for linux-phy@lists.infradead.org; Sat, 14 Nov 2026 11:55:50 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id D0A0261DA5; Sat, 14 Nov 2026 11:55:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 154761F000C5; Sat, 14 Nov 2026 11:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794657349; bh=4/Q1bfzHfAdx4wt2Qbi+egQJKxl84zjDLUbFA3DRoSQ=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=Zahy/hNqmGQJOjs0QgTtqR8oGTtXJ8fNe5guB89mnjz002biupVowEMq5Olf9oKih EcAZTHdMEh4ao5TZTLh6LffeRBb7mqdcbjqrJgW8itLPuipSP8DWSd3NAcu/pGg1wz sM23i6E3/aEJoLbxbMdLa3+U473hiGJ36YmDxzpeaAMh4wZ/p8AJjAklz/HwQuPKK4 93LFjDFsj//Y5jevCVR5VujtQNbRkXuUVd3RD5cGvhxsXuwFX5TQ1i4qElFFiehuu8 XrhGazTCUy89P/71Q3rWi8gM5T/q8F8LUmoh9J+mv3ZJg+VxBD/PTgGJQpwRX7OVZW BWudybVwsq0LQ== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH v7 10/23] media: qcom: camss: csid: Add support for CSID 980 To: "Wenmeng Liu" Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, media-ci@linuxtv.org, vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com In-Reply-To: <20261114-add-support-for-camss-on-sm8750-v7-10-8ff2a11835f6@oss.qualcomm.com> References: <20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com> <20261114-add-support-for-camss-on-sm8750-v7-10-8ff2a11835f6@oss.qualcomm.com> Date: Sat, 14 Nov 2026 11:55:48 +0000 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MyBwb3RlbnRpYWwKaXNzdWVzIHRvIGNvbnNpZGVyOgotIFtIaWdoXSBtZWRpYTogcWNvbTogY2Ft c3M6IHdyb25nIGR0X2lkIGNhbGN1bGF0aW9uIGluCiAgX19jc2lkX2NvbmZpZ3VyZV9yZGlfc3Ry ZWFtKCkKLSBbTWVkaXVtXSBtZWRpYTogcWNvbTogY2Ftc3M6IG1pc3BsYWNlZCBsYW5lX2NudCBm YWxsYmFjayBpbgogIGNhbXNzLWNzaWQtOTgwLmMKLSBbTWVkaXVtXSBtZWRpYTogcWNvbTogY2Ft c3M6IHJhY2Ugb24gY3NpZC0+cmVnX3VwZGF0ZSBhbmQgYWRkcl91cGRhdGUKICBpbiBjc2lkLTk4 MAotLQoKY29tbWl0IGFkMWZmN2ZhMjYxMjBiY2QyMDA1YzhjZjY5ZDgxNjU5OWQ5NDg5OGYKQXV0 aG9yOiBIYW5neGlhbmcgTWEgPGhhbmd4aWFuZy5tYUBvc3MucXVhbGNvbW0uY29tPgoKbWVkaWE6 IHFjb206IGNhbXNzOiBjc2lkOiBBZGQgc3VwcG9ydCBmb3IgQ1NJRCA5ODAKClRoaXMgY29tbWl0 IGFkZHMgdGhlIENTSUQgOTgwIGhhcmR3YXJlIG9wZXJhdGlvbnMgZHJpdmVyIGFuZCBwb3B1bGF0 ZXMKdGhlIFNNODc1MCBDU0lEIHN1YmRldmljZSByZXNvdXJjZSBkZWZpbml0aW9ucy4KCj4gZGlm ZiAtLWdpdCBhL2RyaXZlcnMvbWVkaWEvcGxhdGZvcm0vcWNvbS9jYW1zcy9jYW1zcy1jc2lkLTk4 MC5jIGIvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2NhbXNzL2NhbXNzLWNzaWQtOTgwLmMK PiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAwMDAwMDAuLjcxM2RiMjVjZDhj NjUKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy9tZWRpYS9wbGF0Zm9ybS9xY29tL2Nh bXNzL2NhbXNzLWNzaWQtOTgwLmMKPiBAQCAtMCwwICsxLDQ2NiBAQAoKWyAuLi4gXQoKPiArc3Rh dGljIHZvaWQgX19jc2lkX2NvbmZpZ3VyZV9yeChzdHJ1Y3QgY3NpZF9kZXZpY2UgKmNzaWQsCj4g KwkJCQlzdHJ1Y3QgY3NpZF9waHlfY29uZmlnICpwaHkpCj4gK3sKPiArCWludCB2YWw7Cj4gKwo+ ICsJdmFsID0gKHBoeS0+bGFuZV9jbnQgLSAxKSA8PCBDU0kyX1JYX0NGRzBfTlVNX0FDVElWRV9M QU5FUzsKPiArCXZhbCB8PSBwaHktPmxhbmVfYXNzaWduIDw8IENTSTJfUlhfQ0ZHMF9ETDBfSU5Q VVRfU0VMOwo+ICsJdmFsIHw9IChwaHktPmNzaXBoeV9pZCArIENTSTJfUlhfQ0ZHMF9QSFlfU0VM X0JBU0VfSURYKQo+ICsJICAgICAgIDw8IENTSTJfUlhfQ0ZHMF9QSFlfTlVNX1NFTDsKPiArCXdy aXRlbCh2YWwsIGNzaWQtPmJhc2UgKyBDU0lEX0NTSTJfUlhfQ0ZHMCk7Cj4gKwo+ICsJdmFsID0g Q1NJMl9SWF9DRkcxX0VDQ19DT1JSRUNUSU9OX0VOOwo+ICsJd3JpdGVsKHZhbCwgY3NpZC0+YmFz ZSArIENTSURfQ1NJMl9SWF9DRkcxKTsKPiArfQoKWyAuLi4gXQoKPiArc3RhdGljIHZvaWQgX19j c2lkX2NvbmZpZ3VyZV9yZGlfc3RyZWFtKHN0cnVjdCBjc2lkX2RldmljZSAqY3NpZCwgdTggZW5h YmxlLCB1OCBwb3J0LCB1OCB2YykKPiArewo+ICsJdTggbGFuZV9jbnQgPSBjc2lkLT5waHkubGFu ZV9jbnQ7Cj4gKwl1MzIgdmFsOwo+ICsKPiArCS8qIFNvdXJjZSBwYWRzIG1hdGNoaW5nIFJESSBj aGFubmVscyBvbiBoYXJkd2FyZS4KPiArCSAqIEUuZy4gUGFkIDEgLT4gUkRJMCwgUGFkIDIgLT4g UkRJMSwgZXRjLgo+ICsJICovCj4gKwlzdHJ1Y3QgdjRsMl9tYnVzX2ZyYW1lZm10ICppbnB1dF9m b3JtYXQgPSAmY3NpZC0+Zm10W01TTV9DU0lEX1BBRF9GSVJTVF9TUkMgKyBwb3J0XTsKPiArCWNv bnN0IHN0cnVjdCBjc2lkX2Zvcm1hdF9pbmZvICpmb3JtYXQgPSBjc2lkX2dldF9mbXRfZW50cnko Y3NpZC0+cmVzLT5mb3JtYXRzLT5mb3JtYXRzLAo+ICsJCQkJCQkJCSAgIGNzaWQtPnJlcy0+Zm9y bWF0cy0+bmZvcm1hdHMsCj4gKwkJCQkJCQkJICAgaW5wdXRfZm9ybWF0LT5jb2RlKTsKPiArCj4g KwlpZiAoIWxhbmVfY250KQo+ICsJCWxhbmVfY250ID0gNDsKCltTZXZlcml0eTogTWVkaXVtXQpX YXMgdGhlIGxhbmVfY250IGZhbGxiYWNrIG1lYW50IHRvIGJlIGluIF9fY3NpZF9jb25maWd1cmVf cngoKSBpbnN0ZWFkIG9mCl9fY3NpZF9jb25maWd1cmVfcmRpX3N0cmVhbSgpPwoKSW4gX19jc2lk X2NvbmZpZ3VyZV9yZGlfc3RyZWFtKCksIGxhbmVfY250IGlzIG5ldmVyIHJlYWQgYWZ0ZXIgYmVp bmcgc2V0LAp3aGljaCB0cmlnZ2VycyBhIC1XdW51c2VkLWJ1dC1zZXQtdmFyaWFibGUgd2Fybmlu ZyB1bmRlciBXPTEgKGFuZCBwcmVjZWRlcwp0aGUgdmFyaWFibGUgZGVjbGFyYXRpb25zIGJlbG93 KS4gIE1lYW53aGlsZSwgX19jc2lkX2NvbmZpZ3VyZV9yeCgpIHVzZXMKcGh5LT5sYW5lX2NudCAt IDEgZGlyZWN0bHkgaW4gc2lnbmVkIGludCBhcml0aG1ldGljLCBzbyBpZiBwaHktPmxhbmVfY250 CmlzIDAgKGZvciBpbnN0YW5jZSwgd2hlbiBjc2lkX3NldF9zdHJlYW0oKSBkaXNhYmxlcyBhIHN0 cmVhbSBhZnRlcgpjc2lkX3NldF9wb3dlcigpIHdpdGhvdXQgYW4gYWN0aXZlIHNpbmsgbGluayks IHZhbCBiZWNvbWVzIC0xIGFuZCBjb3JydXB0cwphbGwgZmllbGRzIHdyaXR0ZW4gdG8gQ1NJRF9D U0kyX1JYX0NGRzAuCgo+ICsKPiArCS8qCj4gKwkgKiBEVF9JRCBpcyBhIHR3byBiaXQgYml0Zmll bGQgdGhhdCBpcyBjb25jYXRlbmF0ZWQgd2l0aAo+ICsJICogdGhlIGZvdXIgbGVhc3Qgc2lnbmlm aWNhbnQgYml0cyBvZiB0aGUgZml2ZSBiaXQgVkMKPiArCSAqIGJpdGZpZWxkIHRvIGdlbmVyYXRl IGFuIGludGVybmFsIENJRCB2YWx1ZS4KPiArCSAqCj4gKwkgKiBDU0lEX1JESV9DRkcwKHZjKQo+ ICsJICogRFRfSUQgOiAyODoyNwo+ICsJICogVkMgICAgOiAyNjoyMgo+ICsJICogRFQgICAgOiAy MToxNgo+ICsJICoKPiArCSAqIENJRCAgIDogVkMgMzowIDw8IDIgfCBEVF9JRCAxOjAKPiArCSAq Lwo+ICsJdTggZHRfaWQgPSB2YyAmIDB4MDM7Cj4gKwl1MzIgcmRpX2NmZzBfb2Zmc2V0ID0gQ1NJ RF9SRElfQ0ZHMChwb3J0KTsKPiArCXUzMiByZGlfY2ZnMV9vZmZzZXQgPSBDU0lEX1JESV9DRkcx KHBvcnQpOwo+ICsJdTMyIHJkaV9jdHJsX29mZnNldCA9IENTSURfUkRJX0NUUkwocG9ydCk7Cj4g Kwo+ICsJdmFsID0gUkRJX0NGRzBfVElNRVNUQU1QX0VOOwo+ICsJdmFsIHw9IFJESV9DRkcwX1RJ TUVTVEFNUF9TVEJfU0VMOwo+ICsJdmFsIHw9IFJESV9DRkcwX1JFVElNRV9CUzsKPiArCj4gKwkv KiBub3RlOiBmb3Igbm9uLVJESSBwYXRoLCB0aGlzIHNob3VsZCBiZSBmb3JtYXQtPmRlY29kZV9m b3JtYXQgKi8KPiArCXZhbCB8PSBERUNPREVfRk9STUFUX1BBWUxPQURfT05MWSA8PCBSRElfQ0ZH MF9ERUNPREVfRk9STUFUOwo+ICsJdmFsIHw9IHZjIDw8IFJESV9DRkcwX1ZDOwo+ICsJdmFsIHw9 IGZvcm1hdC0+ZGF0YV90eXBlIDw8IFJESV9DRkcwX0RUOwo+ICsJdmFsIHw9IGR0X2lkIDw8IFJE SV9DRkcwX0RUX0lEOwo+ICsJd3JpdGVsKHZhbCwgY3NpZC0+YmFzZSArIHJkaV9jZmcwX29mZnNl dCk7CgpbIC4uLiBdCgo+ICtzdGF0aWMgdm9pZCBjc2lkX2NvbmZpZ3VyZV9zdHJlYW0oc3RydWN0 IGNzaWRfZGV2aWNlICpjc2lkLCB1OCBlbmFibGUpCj4gK3sKPiArCXU4IGksIGs7Cj4gKwo+ICsJ X19jc2lkX2NvbmZpZ3VyZV9yeChjc2lkLCAmY3NpZC0+cGh5KTsKPiArCj4gKwlmb3IgKGkgPSAw OyBpIDwgTVNNX0NTSURfTUFYX1NSQ19TVFJFQU1TXzk4MDsgaSsrKSB7Cj4gKwkJaWYgKGNzaWQt PnBoeS5lbl92YyAmIEJJVChpKSkgewo+ICsJCQlfX2NzaWRfY29uZmlndXJlX3JkaV9zdHJlYW0o Y3NpZCwgZW5hYmxlLCBpLCAwKTsKCltTZXZlcml0eTogSGlnaF0KU2hvdWxkIGR0X2lkIGluIF9f Y3NpZF9jb25maWd1cmVfcmRpX3N0cmVhbSgpIGJlIGRlcml2ZWQgZnJvbSBwb3J0ICYgMHgwMwpy YXRoZXIgdGhhbiB2YyAmIDB4MDM/Cgpjc2lkX2NvbmZpZ3VyZV9zdHJlYW0oKSBhbHdheXMgcGFz c2VzIHZjID0gMCB3aGlsZSBwYXNzaW5nIHRoZSBSREkgY2hhbm5lbAppbmRleCBpIGFzIHBvcnQu ICBDYWxjdWxhdGluZyBkdF9pZCBmcm9tIHZjIHNldHMgUkRJX0NGRzBfRFRfSUQgdG8gMCBmb3IK ZXZlcnkgUkRJIGNoYW5uZWwsIHNvIFJESTEsIFJESTIsIGFuZCBSREkzIGFsbCByZWNlaXZlIGlu dGVybmFsIENJRCAwIGFuZApjYW5ub3Qgc3RyZWFtIHByb3Blcmx5LCBtYXRjaGluZyB0aGUgaXNz dWUgZml4ZWQgZm9yIENTSUQgR0VOMyBpbiBjb21taXQKYWQxMzZlNTI2MzRkICgibWVkaWE6IHFj b206IGNhbXNzOiBGaXggUkRJIHN0cmVhbWluZyBmb3IgQ1NJRCBHRU4zIikgYW5kCmZvciBDU0lE IEdFTjIgaW4gY29tbWl0IDYxODc2NTYzNGNlZiAoIm1lZGlhOiBxY29tOiBjYW1zczogRml4IFJE SQpzdHJlYW1pbmcgZm9yIENTSUQgR0VOMiIpLgoKWyAuLi4gXQoKPiArc3RhdGljIGlycXJldHVy bl90IGNzaWRfaXNyKGludCBpcnEsIHZvaWQgKmRldikKPiArewo+ICsJc3RydWN0IGNzaWRfZGV2 aWNlICpjc2lkID0gZGV2Owo+ICsJdTMyIHZhbCwgYnVmX2RvbmVfdmFsOwo+ICsJdTggcmVzZXRf ZG9uZTsKPiArCWludCBpOwo+ICsKPiArCXZhbCA9IHJlYWRsKGNzaWQtPmJhc2UgKyBDU0lEX1RP UF9JUlFfU1RBVFVTKTsKPiArCXdyaXRlbCh2YWwsIGNzaWQtPmJhc2UgKyBDU0lEX1RPUF9JUlFf Q0xFQVIpOwo+ICsKPiArCXJlc2V0X2RvbmUgPSB2YWwgJiBJTkZPX1JTVF9ET05FOwo+ICsKPiAr CWJ1Zl9kb25lX3ZhbCA9IHJlYWRsKGNzaWQtPmJhc2UgKyBDU0lEX0JVRl9ET05FX0lSUV9TVEFU VVMpOwo+ICsJd3JpdGVsKGJ1Zl9kb25lX3ZhbCwgY3NpZC0+YmFzZSArIENTSURfQlVGX0RPTkVf SVJRX0NMRUFSKTsKPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgTVNNX0NTSURfTUFYX1NSQ19TVFJF QU1TXzk4MDsgaSsrKSB7Cj4gKwkJaWYgKGNzaWQtPnBoeS5lbl92YyAmIEJJVChpKSkgewo+ICsJ CQl2YWwgPSByZWFkbChjc2lkLT5iYXNlICsgQ1NJRF9DU0kyX1JESU5fSVJRX1NUQVRVUyhpKSk7 Cj4gKwkJCXdyaXRlbCh2YWwsIGNzaWQtPmJhc2UgKyBDU0lEX0NTSTJfUkRJTl9JUlFfQ0xFQVIo aSkpOwo+ICsKPiArCQkJaWYgKHZhbCAmIElORk9fUlVQX0RPTkUpIHsKPiArCQkJCV9fY3NpZF9h ZGRyX3VwZGF0ZV9jbGVhcihjc2lkLCBpKTsKPiArCQkJCV9fY3NpZF9yZWdfdXBkYXRlX2NsZWFy KGNzaWQsIGkpOwo+ICsJCQl9Cj4gKwo+ICsJCQlpZiAoYnVmX2RvbmVfdmFsICYgQklUKEJVRl9E T05FX0lSUV9TVEFUVVNfUkRJX09GRlNFVCArIGkpKQo+ICsJCQkJY2Ftc3NfYnVmX2RvbmUoY3Np ZC0+Y2Ftc3MsIGNzaWQtPmlkLCBpKTsKPiArCQl9Cj4gKwl9CgpbU2V2ZXJpdHk6IE1lZGl1bV0K Q2FuIF9fY3NpZF9hZGRyX3VwZGF0ZV9jbGVhcigpIGFuZCBfX2NzaWRfcmVnX3VwZGF0ZV9jbGVh cigpIGluIGNzaWRfaXNyKCkKcmFjZSB3aXRoIGNvbmN1cnJlbnQgdXBkYXRlcyB0byBjc2lkLT5y ZWdfdXBkYXRlIGFuZCBjc2lkLT5hZGRyX3VwZGF0ZT8KCkluIGNhbXNzLXZmZS5jLCB2ZmVfcXVl dWVfYnVmZmVyX3YyKCksIHZmZV9lbmFibGVfb3V0cHV0X3YyKCksIGFuZAp2ZmVfYnVmX2RvbmUo KSBob2xkIHZmZS0+b3V0cHV0X2xvY2sgd2hpbGUgY2FsbGluZyB0aGUgQ1NJRCBhZGRyX3VwZGF0 ZQphbmQgcmVnX3VwZGF0ZSBjYWxsYmFja3MsIHdoaWNoIHBlcmZvcm0gbm9uLWF0b21pYyByZWFk LW1vZGlmeS13cml0ZQp1cGRhdGVzIG9uIGNzaWQtPnJlZ191cGRhdGUgYW5kIGNzaWQtPmFkZHJf dXBkYXRlLiAgSG93ZXZlciwgY3NpZF9pc3IoKQpjbGVhcnMgYml0cyBpbiBjc2lkLT5hZGRyX3Vw ZGF0ZSBhbmQgY3NpZC0+cmVnX3VwZGF0ZSBiZWZvcmUKY2Ftc3NfYnVmX2RvbmUoKSBpcyBjYWxs ZWQgYW5kIHdpdGhvdXQgaG9sZGluZyB2ZmUtPm91dHB1dF9sb2NrOgoKQ1BVMCAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgIENQVTEgKDxoYXJkaXJxPikKdmZlX3F1ZXVlX2J1ZmZlcl92Migp CiAgc3Bpbl9sb2NrX2lycXNhdmUoJnZmZS0+b3V0cHV0X2xvY2spCiAgX19jc2lkX2FkZHJfdXBk YXRlKGNzaWQsIGkpCiAgICBjc2lkLT5yZWdfdXBkYXRlIHw9IEFVUF9SREkoaSkKICAgIHdyaXRl bChjc2lkLT5yZWdfdXBkYXRlLAogICAgICAgICAgIENTSURfTElURV9SVVBfQVVQX0NNRCkKICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGNzaWRfaXNyKCkKICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgaWYgKHZhbCAmIElORk9fUlVQX0RPTkUpCiAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgX19jc2lkX2FkZHJfdXBkYXRlX2NsZWFyKGNzaWQs IGkpCiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBjc2lkLT5yZWdfdXBk YXRlICY9IH5BVVBfUkRJKGkpCiAgX19jc2lkX3JlZ191cGRhdGUoY3NpZCwgaSkKICAgIGNzaWQt PnJlZ191cGRhdGUgfD0gUlVQX1JESShpKQogICAgd3JpdGVsKGNzaWQtPnJlZ191cGRhdGUsIC4u LikgPC0tIG92ZXJ3cml0ZXMgQ01EIHdpdGggQVVQX1JESShpKSBjbGVhcmVkCgpPbiBDU0lEIExp dGUsIHdoZXJlIFJVUCBhbmQgQVVQIHNoYXJlIGNzaWQtPnJlZ191cGRhdGUgYW5kIHRoZQpDU0lE X0xJVEVfUlVQX0FVUF9DTUQgcmVnaXN0ZXIsIHRoaXMgcmFjZSBjYW4gY2xlYXIgYSBuZXdseSBx dWV1ZWQgQVVQIGJpdAppbiBoYXJkd2FyZSBiZWZvcmUgaXQgaXMgY29uc3VtZWQsIGFuZCBhY3Jv c3MgbXVsdGlwbGUgYWN0aXZlIFJESSBwb3J0cyBpdApjYW4gbG9zZSBvciByZXRhaW4gc3RhbGUg dXBkYXRlIGJpdHMgaW4gY3NpZC0+cmVnX3VwZGF0ZSBhbmQKY3NpZC0+YWRkcl91cGRhdGUuCgot LSAKU2FzaGlrbyBBSSByZXZpZXcgwrcgaHR0cHM6Ly9zYXNoaWtvLmRldi8jL3BhdGNoc2V0LzIw MjYxMTE0LWFkZC1zdXBwb3J0LWZvci1jYW1zcy1vbi1zbTg3NTAtdjctMC04ZmYyYTExODM1ZjZA b3NzLnF1YWxjb21tLmNvbT9wYXJ0PTEwCgotLSAKbGludXgtcGh5IG1haWxpbmcgbGlzdApsaW51 eC1waHlAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwczovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1waHkK