From: "tip-bot for Yan, Zheng" <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: zheng.z.yan@intel.com, linux-kernel@vger.kernel.org,
kan.liang@intel.com, acme@kernel.org, tglx@linutronix.de,
peterz@infradead.org, hpa@zytor.com, mingo@kernel.org,
vincent.weaver@maine.edu, torvalds@linux-foundation.org,
paulus@samba.org, luto@amacapital.net
Subject: [tip:perf/core] perf/x86/intel: Use context switch callback to flush LBR stack
Date: Wed, 18 Feb 2015 09:14:31 -0800 [thread overview]
Message-ID: <tip-2a0ad3b326a9024ba86dca4028499d31fa0c6c4d@git.kernel.org> (raw)
In-Reply-To: <1415156173-10035-4-git-send-email-kan.liang@intel.com>
Commit-ID: 2a0ad3b326a9024ba86dca4028499d31fa0c6c4d
Gitweb: http://git.kernel.org/tip/2a0ad3b326a9024ba86dca4028499d31fa0c6c4d
Author: Yan, Zheng <zheng.z.yan@intel.com>
AuthorDate: Tue, 4 Nov 2014 21:55:59 -0500
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 18 Feb 2015 17:16:03 +0100
perf/x86/intel: Use context switch callback to flush LBR stack
Previous commit introduces context switch callback, its function
overlaps with the flush branch stack callback. So we can use the
context switch callback to flush LBR stack.
This patch adds code that uses the flush branch callback to
flush the LBR stack when task is being scheduled in. The callback
is enabled only when there are events use the LBR hardware. This
patch also removes all old flush branch stack code.
Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: eranian@google.com
Cc: jolsa@redhat.com
Link: http://lkml.kernel.org/r/1415156173-10035-4-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/perf_event.c | 7 ---
arch/x86/kernel/cpu/perf_event.h | 3 +-
arch/x86/kernel/cpu/perf_event_intel.c | 14 +-----
arch/x86/kernel/cpu/perf_event_intel_lbr.c | 27 +++++++++++
include/linux/perf_event.h | 1 -
kernel/events/core.c | 77 ------------------------------
6 files changed, 30 insertions(+), 99 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 0efbd6c..6b1fd26 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1920,12 +1920,6 @@ static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
x86_pmu.sched_task(ctx, sched_in);
}
-static void x86_pmu_flush_branch_stack(void)
-{
- if (x86_pmu.flush_branch_stack)
- x86_pmu.flush_branch_stack();
-}
-
void perf_check_microcode(void)
{
if (x86_pmu.check_microcode)
@@ -1955,7 +1949,6 @@ static struct pmu pmu = {
.commit_txn = x86_pmu_commit_txn,
.event_idx = x86_pmu_event_idx,
- .flush_branch_stack = x86_pmu_flush_branch_stack,
.sched_task = x86_pmu_sched_task,
};
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 211b54c..949d008 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -472,7 +472,6 @@ struct x86_pmu {
void (*cpu_dead)(int cpu);
void (*check_microcode)(void);
- void (*flush_branch_stack)(void);
void (*sched_task)(struct perf_event_context *ctx,
bool sched_in);
@@ -733,6 +732,8 @@ void intel_pmu_pebs_disable_all(void);
void intel_ds_init(void);
+void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
+
void intel_pmu_lbr_reset(void);
void intel_pmu_lbr_enable(struct perf_event *event);
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 498b6d9..424fbf7 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2044,18 +2044,6 @@ static void intel_pmu_cpu_dying(int cpu)
fini_debug_store_on_cpu(cpu);
}
-static void intel_pmu_flush_branch_stack(void)
-{
- /*
- * Intel LBR does not tag entries with the
- * PID of the current task, then we need to
- * flush it on ctxsw
- * For now, we simply reset it
- */
- if (x86_pmu.lbr_nr)
- intel_pmu_lbr_reset();
-}
-
PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
PMU_FORMAT_ATTR(ldlat, "config1:0-15");
@@ -2107,7 +2095,7 @@ static __initconst const struct x86_pmu intel_pmu = {
.cpu_starting = intel_pmu_cpu_starting,
.cpu_dying = intel_pmu_cpu_dying,
.guest_get_msrs = intel_guest_get_msrs,
- .flush_branch_stack = intel_pmu_flush_branch_stack,
+ .sched_task = intel_pmu_lbr_sched_task,
};
static __init void intel_clovertown_quirk(void)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 8bc078f..c0e23c5 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -177,6 +177,31 @@ void intel_pmu_lbr_reset(void)
intel_pmu_lbr_reset_64();
}
+void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+
+ if (!x86_pmu.lbr_nr)
+ return;
+
+ /*
+ * When sampling the branck stack in system-wide, it may be
+ * necessary to flush the stack on context switch. This happens
+ * when the branch stack does not tag its entries with the pid
+ * of the current task. Otherwise it becomes impossible to
+ * associate a branch entry with a task. This ambiguity is more
+ * likely to appear when the branch stack supports priv level
+ * filtering and the user sets it to monitor only at the user
+ * level (which could be a useful measurement in system-wide
+ * mode). In that case, the risk is high of having a branch
+ * stack with branch from multiple tasks.
+ */
+ if (sched_in) {
+ intel_pmu_lbr_reset();
+ cpuc->lbr_context = ctx;
+ }
+}
+
void intel_pmu_lbr_enable(struct perf_event *event)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -195,6 +220,7 @@ void intel_pmu_lbr_enable(struct perf_event *event)
cpuc->br_sel = event->hw.branch_reg.reg;
cpuc->lbr_users++;
+ perf_sched_cb_inc(event->ctx->pmu);
}
void intel_pmu_lbr_disable(struct perf_event *event)
@@ -206,6 +232,7 @@ void intel_pmu_lbr_disable(struct perf_event *event)
cpuc->lbr_users--;
WARN_ON_ONCE(cpuc->lbr_users < 0);
+ perf_sched_cb_dec(event->ctx->pmu);
if (cpuc->enabled && !cpuc->lbr_users) {
__intel_pmu_lbr_disable();
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index fbab623..c7007a5 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -511,7 +511,6 @@ struct perf_event_context {
u64 generation;
int pin_count;
int nr_cgroups; /* cgroup evts */
- int nr_branch_stack; /* branch_stack evt */
struct rcu_head rcu_head;
struct delayed_work orphans_remove;
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 6c8b31b..f563ce7 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -153,7 +153,6 @@ enum event_type_t {
*/
struct static_key_deferred perf_sched_events __read_mostly;
static DEFINE_PER_CPU(atomic_t, perf_cgroup_events);
-static DEFINE_PER_CPU(atomic_t, perf_branch_stack_events);
static DEFINE_PER_CPU(int, perf_sched_cb_usages);
static atomic_t nr_mmap_events __read_mostly;
@@ -1240,9 +1239,6 @@ list_add_event(struct perf_event *event, struct perf_event_context *ctx)
if (is_cgroup_event(event))
ctx->nr_cgroups++;
- if (has_branch_stack(event))
- ctx->nr_branch_stack++;
-
list_add_rcu(&event->event_entry, &ctx->event_list);
ctx->nr_events++;
if (event->attr.inherit_stat)
@@ -1409,9 +1405,6 @@ list_del_event(struct perf_event *event, struct perf_event_context *ctx)
cpuctx->cgrp = NULL;
}
- if (has_branch_stack(event))
- ctx->nr_branch_stack--;
-
ctx->nr_events--;
if (event->attr.inherit_stat)
ctx->nr_stat--;
@@ -2809,64 +2802,6 @@ static void perf_event_context_sched_in(struct perf_event_context *ctx,
}
/*
- * When sampling the branck stack in system-wide, it may be necessary
- * to flush the stack on context switch. This happens when the branch
- * stack does not tag its entries with the pid of the current task.
- * Otherwise it becomes impossible to associate a branch entry with a
- * task. This ambiguity is more likely to appear when the branch stack
- * supports priv level filtering and the user sets it to monitor only
- * at the user level (which could be a useful measurement in system-wide
- * mode). In that case, the risk is high of having a branch stack with
- * branch from multiple tasks. Flushing may mean dropping the existing
- * entries or stashing them somewhere in the PMU specific code layer.
- *
- * This function provides the context switch callback to the lower code
- * layer. It is invoked ONLY when there is at least one system-wide context
- * with at least one active event using taken branch sampling.
- */
-static void perf_branch_stack_sched_in(struct task_struct *prev,
- struct task_struct *task)
-{
- struct perf_cpu_context *cpuctx;
- struct pmu *pmu;
- unsigned long flags;
-
- /* no need to flush branch stack if not changing task */
- if (prev == task)
- return;
-
- local_irq_save(flags);
-
- rcu_read_lock();
-
- list_for_each_entry_rcu(pmu, &pmus, entry) {
- cpuctx = this_cpu_ptr(pmu->pmu_cpu_context);
-
- /*
- * check if the context has at least one
- * event using PERF_SAMPLE_BRANCH_STACK
- */
- if (cpuctx->ctx.nr_branch_stack > 0
- && pmu->flush_branch_stack) {
-
- perf_ctx_lock(cpuctx, cpuctx->task_ctx);
-
- perf_pmu_disable(pmu);
-
- pmu->flush_branch_stack();
-
- perf_pmu_enable(pmu);
-
- perf_ctx_unlock(cpuctx, cpuctx->task_ctx);
- }
- }
-
- rcu_read_unlock();
-
- local_irq_restore(flags);
-}
-
-/*
* Called from scheduler to add the events of the current task
* with interrupts disabled.
*
@@ -2898,10 +2833,6 @@ void __perf_event_task_sched_in(struct task_struct *prev,
if (atomic_read(this_cpu_ptr(&perf_cgroup_events)))
perf_cgroup_sched_in(prev, task);
- /* check for system-wide branch_stack events */
- if (atomic_read(this_cpu_ptr(&perf_branch_stack_events)))
- perf_branch_stack_sched_in(prev, task);
-
if (__this_cpu_read(perf_sched_cb_usages))
perf_pmu_sched_task(prev, task, true);
}
@@ -3480,10 +3411,6 @@ static void unaccount_event_cpu(struct perf_event *event, int cpu)
if (event->parent)
return;
- if (has_branch_stack(event)) {
- if (!(event->attach_state & PERF_ATTACH_TASK))
- atomic_dec(&per_cpu(perf_branch_stack_events, cpu));
- }
if (is_cgroup_event(event))
atomic_dec(&per_cpu(perf_cgroup_events, cpu));
}
@@ -7139,10 +7066,6 @@ static void account_event_cpu(struct perf_event *event, int cpu)
if (event->parent)
return;
- if (has_branch_stack(event)) {
- if (!(event->attach_state & PERF_ATTACH_TASK))
- atomic_inc(&per_cpu(perf_branch_stack_events, cpu));
- }
if (is_cgroup_event(event))
atomic_inc(&per_cpu(perf_cgroup_events, cpu));
}
next prev parent reply other threads:[~2015-02-18 17:15 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-05 2:55 [PATCH V7 00/17] perf, x86: Haswell LBR call stack support Kan Liang
2014-11-05 2:55 ` [PATCH V7 01/17] perf, x86: Reduce lbr_sel_map size Kan Liang
2015-02-18 17:13 ` [tip:perf/core] perf/x86/intel: Reduce lbr_sel_map[] size tip-bot for Yan, Zheng
2014-11-05 2:55 ` [PATCH V7 02/17] perf, core: introduce pmu context switch callback Kan Liang
2015-02-18 17:14 ` [tip:perf/core] perf: Introduce " tip-bot for Yan, Zheng
2014-11-05 2:55 ` [PATCH V7 03/17] perf, x86: use context switch callback to flush LBR stack Kan Liang
2015-02-18 17:14 ` tip-bot for Yan, Zheng [this message]
2014-11-05 2:56 ` [PATCH V7 04/17] perf, x86: Basic Haswell LBR call stack support Kan Liang
2015-02-18 17:14 ` [tip:perf/core] perf/x86/intel: Add basic " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 05/17] perf, core: pmu specific data for perf task context Kan Liang
2015-02-18 17:15 ` [tip:perf/core] perf: Add " tip-bot for Yan, Zheng
2015-12-09 8:34 ` Peter Zijlstra
2015-12-09 14:59 ` Liang, Kan
2015-12-09 15:14 ` Peter Zijlstra
2015-12-09 15:25 ` Liang, Kan
2014-11-05 2:56 ` [PATCH V7 06/17] perf, core: always switch pmu specific data during context switch Kan Liang
2015-02-18 17:15 ` [tip:perf/core] perf: Always " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 07/17] perf, x86: allocate space for storing LBR stack Kan Liang
2015-02-18 17:15 ` [tip:perf/core] perf/x86/intel: Allocate " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 08/17] perf, x86: track number of events that use LBR callstack Kan Liang
2015-02-18 17:15 ` [tip:perf/core] perf/x86/intel: Track number of events that use the " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 09/17] perf, x86: Save/resotre LBR stack during context switch Kan Liang
2015-02-18 17:16 ` [tip:perf/core] perf/x86/intel: Save/ restore " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 10/17] perf, core: simplify need branch stack check Kan Liang
2015-02-18 17:16 ` [tip:perf/core] perf: Simplify the " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 11/17] perf, core: expose LBR call stack to user perf tool Kan Liang
2014-11-05 9:20 ` Peter Zijlstra
2014-11-05 2:56 ` [PATCH V7 12/17] perf, x86: re-organize code that implicitly enables LBR/PEBS Kan Liang
2015-02-18 17:16 ` [tip:perf/core] perf/x86/intel: Re-organize " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 13/17] perf, x86: enable LBR callstack when recording callchain Kan Liang
2014-11-05 9:21 ` Peter Zijlstra
2014-11-05 9:58 ` Stephane Eranian
2014-11-05 10:43 ` Peter Zijlstra
2014-11-05 10:57 ` Stephane Eranian
2014-11-05 12:49 ` Peter Zijlstra
2014-11-05 13:22 ` Stephane Eranian
2014-11-05 15:45 ` Peter Zijlstra
2014-11-05 15:53 ` Liang, Kan
2014-11-05 16:29 ` Peter Zijlstra
2014-11-05 17:52 ` Andi Kleen
2014-11-05 17:57 ` Andi Kleen
2014-11-05 17:40 ` Andi Kleen
2014-11-05 2:56 ` [PATCH V7 14/17] perf, x86: disable FREEZE_LBRS_ON_PMI when LBR operates in callstack mode Kan Liang
2015-02-18 17:17 ` [tip:perf/core] perf/x86/intel: Disable " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 15/17] perf, x86: Discard zero length call entries in LBR call stack Kan Liang
2015-02-18 17:17 ` [tip:perf/core] perf/x86/intel: " tip-bot for Yan, Zheng
2014-11-05 2:56 ` [PATCH V7 16/17] perf tools: handle LBR call stack data Kan Liang
2014-11-05 2:56 ` [PATCH V7 17/17] perf tools: choose to dump callchain from LBR and FP Kan Liang
2014-11-05 9:37 ` [PATCH V7 00/17] perf, x86: Haswell LBR call stack support Peter Zijlstra
2014-11-05 16:22 ` Liang, Kan
2014-11-05 16:27 ` Peter Zijlstra
2014-11-05 17:02 ` Liang, Kan
2015-02-18 17:17 ` [tip:perf/core] perf/x86/intel: Expose LBR callstack to user space tooling tip-bot for Peter Zijlstra
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