From: tip-bot for Andreas Herrmann <andreas.herrmann3@amd.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@redhat.com,
andreas.herrmann3@amd.com, tglx@linutronix.de,
hpa@linux.intel.com
Subject: [tip:x86/amd-nb] x86, cacheinfo: Fix dependency of AMD L3 CID
Date: Fri, 17 Sep 2010 22:55:01 GMT [thread overview]
Message-ID: <tip-3518dd14ca888085797ca8d3a9e11c8ef9e7ae68@git.kernel.org> (raw)
In-Reply-To: <20100917160744.GF4958@loge.amd.com>
Commit-ID: 3518dd14ca888085797ca8d3a9e11c8ef9e7ae68
Gitweb: http://git.kernel.org/tip/3518dd14ca888085797ca8d3a9e11c8ef9e7ae68
Author: Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Fri, 17 Sep 2010 18:07:45 +0200
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Fri, 17 Sep 2010 13:25:56 -0700
x86, cacheinfo: Fix dependency of AMD L3 CID
L3 cache index disable code uses PCI accesses to AMD northbridge functions.
Currently the code is #ifdef CONFIG_CPU_SUP_AMD.
But it should be #if (defined(CONFIG_CPU_SUP_AMD) && defined(CONFIG_PCI))
which in the end is a dependency to K8_NB.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100917160744.GF4958@loge.amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 898c2f4..2521cdc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -306,7 +306,7 @@ struct _cache_attr {
ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
};
-#ifdef CONFIG_CPU_SUP_AMD
+#ifdef CONFIG_K8_NB
/*
* L3 cache descriptors
@@ -556,12 +556,12 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
show_cache_disable_1, store_cache_disable_1);
-#else /* CONFIG_CPU_SUP_AMD */
+#else /* CONFIG_K8_NB */
static void __cpuinit
amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
{
};
-#endif /* CONFIG_CPU_SUP_AMD */
+#endif /* CONFIG_K8_NB */
static int
__cpuinit cpuid4_cache_lookup_regs(int index,
@@ -1000,7 +1000,7 @@ static struct attribute *default_attrs[] = {
static struct attribute *default_l3_attrs[] = {
DEFAULT_SYSFS_CACHE_ATTRS,
-#ifdef CONFIG_CPU_SUP_AMD
+#ifdef CONFIG_K8_NB
&cache_disable_0.attr,
&cache_disable_1.attr,
#endif
prev parent reply other threads:[~2010-09-17 22:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-09-17 15:59 [PATCH 0/3 resend] x86: misc K8_NB updates Andreas Herrmann
2010-09-17 16:02 ` [PATCH 2/3] x86, k8-gart: Decouple handling of garts and northbridges Andreas Herrmann
2010-09-17 22:55 ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann
2010-09-17 16:03 ` [PATCH 3/3] x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB Andreas Herrmann
2010-09-17 22:55 ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann
2010-09-20 21:25 ` tip-bot for Andreas Herrmann
2010-09-17 16:05 ` [PATCH 0/3 resend] x86: misc K8_NB updates Andreas Herrmann
2010-09-17 16:07 ` [PATCH 1/3] x86, cacheinfo: Fix dependency of AMD L3 CID Andreas Herrmann
2010-09-17 22:55 ` tip-bot for Andreas Herrmann [this message]
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