From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752269AbdGAI5M (ORCPT ); Sat, 1 Jul 2017 04:57:12 -0400 Received: from terminus.zytor.com ([65.50.211.136]:33875 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751754AbdGAI5L (ORCPT ); Sat, 1 Jul 2017 04:57:11 -0400 Date: Sat, 1 Jul 2017 01:56:01 -0700 From: tip-bot for Adrian Hunter Message-ID: Cc: adrian.hunter@intel.com, acme@redhat.com, linux-kernel@vger.kernel.org, hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, ak@linux.intel.com Reply-To: tglx@linutronix.de, mingo@kernel.org, ak@linux.intel.com, adrian.hunter@intel.com, acme@redhat.com, linux-kernel@vger.kernel.org, hpa@zytor.com In-Reply-To: <1495786658-18063-37-git-send-email-adrian.hunter@intel.com> References: <1495786658-18063-37-git-send-email-adrian.hunter@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf intel-pt: Do not use TSC packets for calculating CPU cycles to TSC Git-Commit-ID: 38b65b0891dc129dc0a5ce148a21c481e667b395 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 38b65b0891dc129dc0a5ce148a21c481e667b395 Gitweb: http://git.kernel.org/tip/38b65b0891dc129dc0a5ce148a21c481e667b395 Author: Adrian Hunter AuthorDate: Fri, 26 May 2017 11:17:37 +0300 Committer: Arnaldo Carvalho de Melo CommitDate: Fri, 30 Jun 2017 11:50:55 -0300 perf intel-pt: Do not use TSC packets for calculating CPU cycles to TSC CBR (core-to-bus ratio) packets provide an indication of CPU frequency. A more accurate measure can be made by counting the cycles (given by CYC packets) in between other timing packets (either MTC or TSC). Using TSC packets has at least 2 issues: 1) timing might have stopped (e.g. mwait) or 2) TSC packets within PSB+ might slip past CYC packets. For now, simply do not use TSC packets for calculating CPU cycles to TSC. That leaves the case where 2 MTC packets are used, otherwise falling back to the CBR value. Signed-off-by: Adrian Hunter Cc: Andi Kleen Link: http://lkml.kernel.org/r/1495786658-18063-37-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/intel-pt-decoder/intel-pt-decoder.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c index 5dea062..aa1593c 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c @@ -711,6 +711,12 @@ static int intel_pt_calc_cyc_cb(struct intel_pt_pkt_info *pkt_info) break; case INTEL_PT_TSC: + /* + * For now, do not support using TSC packets - refer + * intel_pt_calc_cyc_to_tsc(). + */ + if (data->from_mtc) + return 1; timestamp = pkt_info->packet.payload | (data->timestamp & (0xffULL << 56)); if (data->from_mtc && timestamp < data->timestamp && @@ -828,6 +834,14 @@ static void intel_pt_calc_cyc_to_tsc(struct intel_pt_decoder *decoder, .cbr_cyc_to_tsc = 0, }; + /* + * For now, do not support using TSC packets for at least the reasons: + * 1) timing might have stopped + * 2) TSC packets within PSB+ can slip against CYC packets + */ + if (!from_mtc) + return; + intel_pt_pkt_lookahead(decoder, intel_pt_calc_cyc_cb, &data); }