From: tip-bot for Dave Hansen <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: mingo@kernel.org, hpa@zytor.com, dvlasenk@redhat.com,
peterz@infradead.org, linux-kernel@vger.kernel.org,
eranian@google.com, jolsa@redhat.com, bp@alien8.de,
luto@amacapital.net, dave.hansen@linux.intel.com,
kan.liang@intel.com, dave@sr71.net, brgerst@gmail.com,
tglx@linutronix.de, alexander.shishkin@linux.intel.com,
acme@redhat.com, torvalds@linux-foundation.org,
vincent.weaver@maine.edu
Subject: [tip:perf/core] perf/x86/intel: Use Intel family macros for core perf events
Date: Wed, 8 Jun 2016 04:00:55 -0700 [thread overview]
Message-ID: <tip-ef5f9f47d4ec4cf42bac48c7c4dafacc1b9f0630@git.kernel.org> (raw)
In-Reply-To: <20160603001929.C5F1C079@viggo.jf.intel.com>
Commit-ID: ef5f9f47d4ec4cf42bac48c7c4dafacc1b9f0630
Gitweb: http://git.kernel.org/tip/ef5f9f47d4ec4cf42bac48c7c4dafacc1b9f0630
Author: Dave Hansen <dave.hansen@linux.intel.com>
AuthorDate: Thu, 2 Jun 2016 17:19:29 -0700
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 8 Jun 2016 12:05:58 +0200
perf/x86/intel: Use Intel family macros for core perf events
Use the new model number macros instead of spelling things out
in the comments.
Note that this is missing a Nehalem model that is mentioned in
intel_idle which is fixed up in a later patch.
The resulting binary (arch/x86/events/intel/core.o) is exactly
the same with and without this patch modulo some harmless changes
to restoring %esi in the return path of functions, even those
untouched by this patch.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Dave Hansen <dave@sr71.net>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: jacob.jun.pan@intel.com
Link: http://lkml.kernel.org/r/20160603001929.C5F1C079@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/core.c | 87 ++++++++++++++++++++++----------------------
1 file changed, 44 insertions(+), 43 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 5081b4c..3ed528c 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -16,6 +16,7 @@
#include <asm/cpufeature.h>
#include <asm/hardirq.h>
+#include <asm/intel-family.h>
#include <asm/apic.h>
#include "../perf_event.h"
@@ -3319,11 +3320,11 @@ static int intel_snb_pebs_broken(int cpu)
u32 rev = UINT_MAX; /* default to broken for unknown models */
switch (cpu_data(cpu).x86_model) {
- case 42: /* SNB */
+ case INTEL_FAM6_SANDYBRIDGE:
rev = 0x28;
break;
- case 45: /* SNB-EP */
+ case INTEL_FAM6_SANDYBRIDGE_X:
switch (cpu_data(cpu).x86_mask) {
case 6: rev = 0x618; break;
case 7: rev = 0x70c; break;
@@ -3573,15 +3574,15 @@ __init int intel_pmu_init(void)
* Install the hw-cache-events table:
*/
switch (boot_cpu_data.x86_model) {
- case 14: /* 65nm Core "Yonah" */
+ case INTEL_FAM6_CORE_YONAH:
pr_cont("Core events, ");
break;
- case 15: /* 65nm Core2 "Merom" */
+ case INTEL_FAM6_CORE2_MEROM:
x86_add_quirk(intel_clovertown_quirk);
- case 22: /* 65nm Core2 "Merom-L" */
- case 23: /* 45nm Core2 "Penryn" */
- case 29: /* 45nm Core2 "Dunnington (MP) */
+ case INTEL_FAM6_CORE2_MEROM_L:
+ case INTEL_FAM6_CORE2_PENRYN:
+ case INTEL_FAM6_CORE2_DUNNINGTON:
memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
@@ -3592,9 +3593,9 @@ __init int intel_pmu_init(void)
pr_cont("Core2 events, ");
break;
- case 30: /* 45nm Nehalem */
- case 26: /* 45nm Nehalem-EP */
- case 46: /* 45nm Nehalem-EX */
+ case INTEL_FAM6_NEHALEM:
+ case INTEL_FAM6_NEHALEM_EP:
+ case INTEL_FAM6_NEHALEM_EX:
memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
@@ -3622,11 +3623,11 @@ __init int intel_pmu_init(void)
pr_cont("Nehalem events, ");
break;
- case 28: /* 45nm Atom "Pineview" */
- case 38: /* 45nm Atom "Lincroft" */
- case 39: /* 32nm Atom "Penwell" */
- case 53: /* 32nm Atom "Cloverview" */
- case 54: /* 32nm Atom "Cedarview" */
+ case INTEL_FAM6_ATOM_PINEVIEW:
+ case INTEL_FAM6_ATOM_LINCROFT:
+ case INTEL_FAM6_ATOM_PENWELL:
+ case INTEL_FAM6_ATOM_CLOVERVIEW:
+ case INTEL_FAM6_ATOM_CEDARVIEW:
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
@@ -3638,9 +3639,9 @@ __init int intel_pmu_init(void)
pr_cont("Atom events, ");
break;
- case 55: /* 22nm Atom "Silvermont" */
- case 76: /* 14nm Atom "Airmont" */
- case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
+ case INTEL_FAM6_ATOM_SILVERMONT1:
+ case INTEL_FAM6_ATOM_SILVERMONT2:
+ case INTEL_FAM6_ATOM_AIRMONT:
memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
@@ -3656,8 +3657,8 @@ __init int intel_pmu_init(void)
pr_cont("Silvermont events, ");
break;
- case 92: /* 14nm Atom "Goldmont" */
- case 95: /* 14nm Atom "Goldmont Denverton" */
+ case INTEL_FAM6_ATOM_GOLDMONT:
+ case INTEL_FAM6_ATOM_DENVERTON:
memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
@@ -3680,9 +3681,9 @@ __init int intel_pmu_init(void)
pr_cont("Goldmont events, ");
break;
- case 37: /* 32nm Westmere */
- case 44: /* 32nm Westmere-EP */
- case 47: /* 32nm Westmere-EX */
+ case INTEL_FAM6_WESTMERE:
+ case INTEL_FAM6_WESTMERE_EP:
+ case INTEL_FAM6_WESTMERE_EX:
memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
@@ -3709,8 +3710,8 @@ __init int intel_pmu_init(void)
pr_cont("Westmere events, ");
break;
- case 42: /* 32nm SandyBridge */
- case 45: /* 32nm SandyBridge-E/EN/EP */
+ case INTEL_FAM6_SANDYBRIDGE:
+ case INTEL_FAM6_SANDYBRIDGE_X:
x86_add_quirk(intel_sandybridge_quirk);
x86_add_quirk(intel_ht_bug);
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
@@ -3723,7 +3724,7 @@ __init int intel_pmu_init(void)
x86_pmu.event_constraints = intel_snb_event_constraints;
x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
- if (boot_cpu_data.x86_model == 45)
+ if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
x86_pmu.extra_regs = intel_snbep_extra_regs;
else
x86_pmu.extra_regs = intel_snb_extra_regs;
@@ -3745,8 +3746,8 @@ __init int intel_pmu_init(void)
pr_cont("SandyBridge events, ");
break;
- case 58: /* 22nm IvyBridge */
- case 62: /* 22nm IvyBridge-EP/EX */
+ case INTEL_FAM6_IVYBRIDGE:
+ case INTEL_FAM6_IVYBRIDGE_X:
x86_add_quirk(intel_ht_bug);
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
@@ -3762,7 +3763,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
x86_pmu.pebs_prec_dist = true;
- if (boot_cpu_data.x86_model == 62)
+ if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
x86_pmu.extra_regs = intel_snbep_extra_regs;
else
x86_pmu.extra_regs = intel_snb_extra_regs;
@@ -3780,10 +3781,10 @@ __init int intel_pmu_init(void)
break;
- case 60: /* 22nm Haswell Core */
- case 63: /* 22nm Haswell Server */
- case 69: /* 22nm Haswell ULT */
- case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
+ case INTEL_FAM6_HASWELL_CORE:
+ case INTEL_FAM6_HASWELL_X:
+ case INTEL_FAM6_HASWELL_ULT:
+ case INTEL_FAM6_HASWELL_GT3E:
x86_add_quirk(intel_ht_bug);
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -3807,10 +3808,10 @@ __init int intel_pmu_init(void)
pr_cont("Haswell events, ");
break;
- case 61: /* 14nm Broadwell Core-M */
- case 86: /* 14nm Broadwell Xeon D */
- case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
- case 79: /* 14nm Broadwell Server */
+ case INTEL_FAM6_BROADWELL_CORE:
+ case INTEL_FAM6_BROADWELL_XEON_D:
+ case INTEL_FAM6_BROADWELL_GT3E:
+ case INTEL_FAM6_BROADWELL_X:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
@@ -3843,7 +3844,7 @@ __init int intel_pmu_init(void)
pr_cont("Broadwell events, ");
break;
- case 87: /* Knights Landing Xeon Phi */
+ case INTEL_FAM6_XEON_PHI_KNL:
memcpy(hw_cache_event_ids,
slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs,
@@ -3861,11 +3862,11 @@ __init int intel_pmu_init(void)
pr_cont("Knights Landing events, ");
break;
- case 142: /* 14nm Kabylake Mobile */
- case 158: /* 14nm Kabylake Desktop */
- case 78: /* 14nm Skylake Mobile */
- case 94: /* 14nm Skylake Desktop */
- case 85: /* 14nm Skylake Server */
+ case INTEL_FAM6_SKYLAKE_MOBILE:
+ case INTEL_FAM6_SKYLAKE_DESKTOP:
+ case INTEL_FAM6_SKYLAKE_X:
+ case INTEL_FAM6_KABYLAKE_MOBILE:
+ case INTEL_FAM6_KABYLAKE_DESKTOP:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
next prev parent reply other threads:[~2016-06-08 11:02 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-03 0:19 [PATCH 01/20] [v2] x86, intel: Introduce macros for Intel family numbers Dave Hansen
2016-06-03 0:19 ` [PATCH 02/20] x86, perf: use Intel family macros for core perf events Dave Hansen
2016-06-08 11:00 ` tip-bot for Dave Hansen [this message]
2016-06-08 14:09 ` [tip:perf/core] perf/x86/intel: Use " Vince Weaver
2016-06-08 14:16 ` Borislav Petkov
2016-06-08 16:25 ` Ingo Molnar
2016-06-08 16:34 ` Borislav Petkov
2016-06-08 19:51 ` Stephane Eranian
2016-06-08 20:15 ` Vince Weaver
2016-06-08 20:48 ` Borislav Petkov
2016-06-03 0:19 ` [PATCH 03/20] x86, rapl: use Intel family macros for rapl Dave Hansen
2016-06-08 11:01 ` [tip:perf/core] perf/x86/rapl: Use Intel family macros for RAPL tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 04/20] x86, intel_idle: use Intel family macros for intel_idle Dave Hansen
2016-06-08 14:14 ` [tip:x86/cpu] x86/intel_idle: Use " tip-bot for Dave Hansen
2016-06-17 2:39 ` [PATCH 04/20] x86, intel_idle: use " Len Brown
2016-06-03 0:19 ` [PATCH 05/20] x86, msr: use Intel family macros for msr events code Dave Hansen
2016-06-08 11:01 ` [tip:perf/core] perf/x86/msr: Use Intel family macros for MSR " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 06/20] x86, msr: add missing Intel models Dave Hansen
2016-06-08 11:02 ` [tip:perf/core] perf/x86/msr: Add " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 07/20] x86, intel: use Intel model macros intead of open-coding Dave Hansen
2016-06-08 14:13 ` [tip:x86/cpu] x86, powercap, rapl: Use " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 08/20] x86, rapl: reorder cpu detection table Dave Hansen
2016-06-08 14:13 ` [tip:x86/cpu] x86, powercap, rapl: Reorder CPU " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 09/20] x86, platform: use new Intel model number macros Dave Hansen
2016-06-08 14:15 ` [tip:x86/cpu] x86/platform: Use " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 10/20] x86, cstate: use Intel Model name macros Dave Hansen
2016-06-08 11:02 ` [tip:perf/core] perf/x86/cstate: Use " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 11/20] x86, uncore: use Intel family name macros for uncore Dave Hansen
2016-06-08 11:03 ` [tip:perf/core] perf/x86/uncore: Use " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 12/20] x86, edac: use Intel family name macros for edac driver Dave Hansen
2016-06-03 0:19 ` [PATCH 13/20] x86, cpufreq: use Intel family name macros for intel_pstate cpufreq driver Dave Hansen
2016-06-08 14:15 ` [tip:x86/cpu] x86/cpufreq: Use Intel family name macros for the " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 14/20] x86, acpi, lss: use Intel family name macros for lpss driver Dave Hansen
2016-06-08 14:16 ` [tip:x86/cpu] x86/acpi/lss: Use Intel family name macros for the acpi_lpss driver tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 15/20] x86, intel_telemetry: use Intel family name macros for telemetry driver Dave Hansen
2016-06-08 14:16 ` [tip:x86/cpu] x86/intel_telemetry: Use " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 16/20] x86, pmc_core: use Intel family name macros for pmc_core driver Dave Hansen
2016-06-08 14:12 ` [tip:perf/core] x86/pmc_core: Use " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 17/20] x86, mmc: use Intel family name macros for mmc driver Dave Hansen
2016-06-08 14:16 ` [tip:x86/cpu] x86, mmc: Use " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 18/20] x86, thermal: clean up and fix cpu model detection for intel_soc_dts_thermal Dave Hansen
2016-06-08 14:17 ` [tip:x86/cpu] x86, thermal: Clean up and fix CPU " tip-bot for Dave Hansen
2016-06-03 0:19 ` [PATCH 19/20] x86, rapl: add Skylake server model detection Dave Hansen
2016-06-08 11:03 ` [tip:perf/core] perf/x86/rapl: Add " tip-bot for Jacob Pan
2016-06-08 14:12 ` Vince Weaver
2016-06-10 12:35 ` Jacob Pan
2016-06-10 15:46 ` Dave Hansen
2016-06-03 0:19 ` [PATCH 20/20] x86, powercap, rapl: add Skylake Server model number Dave Hansen
2016-06-08 14:14 ` [tip:x86/cpu] x86, powercap, rapl: Add " tip-bot for Dave Hansen
2016-06-03 0:38 ` [PATCH 01/20] [v2] x86, intel: Introduce macros for Intel family numbers Rafael J. Wysocki
2016-06-08 9:56 ` [tip:x86/urgent] x86/cpu/intel: " tip-bot for Dave Hansen
2016-06-08 10:03 ` tip-bot for Dave Hansen
2016-06-08 11:01 ` [PATCH 01/20] [v2] x86, intel: " Ingo Molnar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=tip-ef5f9f47d4ec4cf42bac48c7c4dafacc1b9f0630@git.kernel.org \
--to=tipbot@zytor.com \
--cc=acme@redhat.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=bp@alien8.de \
--cc=brgerst@gmail.com \
--cc=dave.hansen@linux.intel.com \
--cc=dave@sr71.net \
--cc=dvlasenk@redhat.com \
--cc=eranian@google.com \
--cc=hpa@zytor.com \
--cc=jolsa@redhat.com \
--cc=kan.liang@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tip-commits@vger.kernel.org \
--cc=luto@amacapital.net \
--cc=mingo@kernel.org \
--cc=peterz@infradead.org \
--cc=tglx@linutronix.de \
--cc=torvalds@linux-foundation.org \
--cc=vincent.weaver@maine.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.