From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Packard Subject: Re: Garbage on screen when switching resolution after BIOS post Date: Tue, 04 Oct 2011 08:38:33 -0700 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2051370539==" Return-path: Received: from keithp.com (home.keithp.com [63.227.221.253]) by gabe.freedesktop.org (Postfix) with ESMTP id EFEF49E7EE for ; Tue, 4 Oct 2011 08:38:36 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: meteor , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============2051370539== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Tue, 4 Oct 2011 17:53:08 +0800, meteor wrote: > Please refer to the VDD power monitoring image: > http://imageshack.us/photo/my-images/827/auoi.jpg/ Nice picture. As Daniel mentioned, you'll want to try my eDP power sequencing changes and see what they do. I'm not sure they will though -- my understanding of the eDP spec is that if we drop VDD, we must hold it low for the specified interval, but I haven't found anything saying that we must lower VDD when disabling and re-enabling the display. Given that the VDD low interval is often quite long (500ms or more), I'd prefer to avoid doing this when booting the operating system. I wonder if the final solution will be to move the whole DP link training and eDP power sequencing stuff to a separate thread to keep that out of the sequential path of the mode setting code which is run when the driver loads. =2D-=20 keith.packard@intel.com --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIVAwUBTosoeTYtFsjWk68qAQg4Fg/+L9T0g0zofHjj8EcFE/W5uwis2qmx/eIx OIQpHbM2vU571Swvz5pw8MkKfbdvC4luPObcPQaKxHFVIL+AueqrdaFywKBFoMhw UJ26PC25i9wnLe8awZezkl0jVxlTzXQUYhSrCpQiC0FyM+lGSyPJkGpNrZdNroNG wXWJ8MLudDDhvWIrv7RTEXOjubOQ4T78eCuETVtXxXD0MUm323/1P/3nGXcyrDDs WkNZIigTkEjBCtq1GCu1GjMPJZHLb0NyLG3wHwgT+ZQZw2NaxD1iTwQ80dZM+EPW urJJJJJds5wqdj8qOcmJ8hKMh/AXbWUi37dMwvHOO4CtITFNPNOEaVvQK4Beelld WMR8kVPILcr0cDCxXzkpbF3ZHsBsyqp9e96SXaINBeuUzkYaZOD0N7BV/XGyl5Oj 8jf16kywo02hEwqGO3Peal6vPk9BxmaGb3cdIdKn2MKoPJudQu0CnJnrjvcjPhLu d9/tyvqRNDtBzWL3OA572Mm+5O2uAGprbkuDnWoGT+lyltt01o4henN5duw5f8cK qc4asiK5bY0S1M0WUZRvd2gsZtt9mPtO+pGpIASawalrnbugdOhtMoSNUNNvxPfk SGrF9+wcHn4pk5YlgZsPQGp5Ehdb4KslMmW2v45Jg19DAiYC3EVLt/PwL5Cml9C9 HDGdy5ZhsZc= =ol8t -----END PGP SIGNATURE----- --=-=-=-- --===============2051370539== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============2051370539==--