From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keith Packard <keithp@keithp.com>
Subject: Re: [PATCH] drm/i915: Reset GMBUS controller after NAK
Date: Wed, 30 Mar 2011 09:48:25 -0700
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References: <1301501231-27133-1-git-send-email-chris@chris-wilson.co.uk>
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On Wed, 30 Mar 2011 17:07:11 +0100, Chris Wilson <chris@chris-wilson.co.uk>=
 wrote:

> +clear_err:
> +	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
> +	POSTING_READ(GMBUS1 + reg_offset);
> +	I915_WRITE(GMBUS1 + reg_offset, 0);

Any posting read needed here?

> +
> +done:
> +	I915_WRITE(GMBUS0 + reg_offset, 0);

What's this new write doing in the non-error path? Do we need a posting
read after it?

=2D-=20
keith.packard@intel.com

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