From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753413AbdGLU42 convert rfc822-to-8bit (ORCPT ); Wed, 12 Jul 2017 16:56:28 -0400 Received: from nat.mansr.com ([81.2.72.238]:36578 "EHLO unicorn.mansr.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753008AbdGLU41 (ORCPT ); Wed, 12 Jul 2017 16:56:27 -0400 X-Greylist: delayed 404 seconds by postgrey-1.27 at vger.kernel.org; Wed, 12 Jul 2017 16:56:27 EDT From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= To: Doug Berger Cc: Thomas Gleixner , Marc Zyngier , Bartosz Golaszewski , Sebastian Frias , Boris Brezillon , open list Subject: Re: [PATCH 1/6] genirq: generic chip: add generic irq_mask_ack functions References: <20170707192016.13001-1-opendmb@gmail.com> <20170707192016.13001-2-opendmb@gmail.com> <4f4c2873-9b24-a544-fc76-b02d6e3f3be3@gmail.com> Date: Wed, 12 Jul 2017 21:49:39 +0100 In-Reply-To: <4f4c2873-9b24-a544-fc76-b02d6e3f3be3@gmail.com> (Doug Berger's message of "Wed, 12 Jul 2017 12:24:30 -0700") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Doug Berger writes: > Mans, as the author of the only existing upstream user of this code, > should have received this as well. > > -Doug > > On 07/07/2017 12:20 PM, Doug Berger wrote: >> The irq_gc_mask_disable_reg_and_ack() function name implies that it >> provides the combined functions of irq_gc_mask_disable_reg() and >> irq_gc_ack(). However, the implementation does not actually do >> that since it writes the mask instead of the disable register. It >> also does not maintain the mask cache which makes it inappropriate >> to use with other masking functions. >> >> In addition, commit 659fb32d1b67 ("genirq: replace irq_gc_ack() with >> {set,clr}_bit variants (fwd)") effectively renamed irq_gc_ack() to >> irq_gc_set_bit() so this function probably should have also been >> renamed at that time. >> >> Since this generic chip code provides three mask functions and two >> ack functions, this commit provides generic implementations for all >> six combinations of the mask and ack functions suitable for use >> with the irq_mask_ack member of the struct irq_chip. >> >> The '_reg' and '_bit' portions of the base function names were left >> out of the new combined function names in an attempt to keep the >> function name lengths manageable with the 80 character source code >> line length while still capturing the distinct aspects of each >> combination of functions. >> >> Signed-off-by: Doug Berger Hmm, something is wrong here. The irq_gc_mask_disable_reg_and_ack() function writes to regs.mask, but the irq-tango driver doesn't set this field (there is no corresponding hardware register). Either it is never called, or the write ends up being harmless. I don't remember why I set irq_mask_ack that way. >> /** >> + * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt >> + * @d: irq_data >> + * >> + * Chip has separate enable/disable registers instead of a single mask >> + * register and pending interrupt is acknowledged by setting a bit. >> + */ >> +void irq_gc_mask_disable_and_ack_set(struct irq_data *d) >> +{ >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); >> + struct irq_chip_type *ct = irq_data_get_chip_type(d); >> + u32 mask = d->mask; >> + >> + irq_gc_lock(gc); >> + irq_reg_writel(gc, mask, ct->regs.disable); >> + *ct->mask_cache &= ~mask; >> + irq_reg_writel(gc, mask, ct->regs.ack); >> + irq_gc_unlock(gc); >> +} This function looks like it should probably be used instead. I'll try to remember to test it when I have time to fire up that hardware. -- Måns Rullgård